#ifndef _L1_S1216x_Defines_H_
#define _L1_S1216x_Defines_H_

//#define USB_Capability
#define CUSTOMER_Capability

#include "si2165defs.h"

#define DVB_T_SCAN_TIMEOUT  4000
#define DVB_T_ADDR_JUMP         0xF4000000
#define DVB_C_ADDR_JUMP         0x00000000
#define DEFAULT_DVB_C_CONSTELLATION constellation_qam256
#define DEFAULT_DVB_C_SYMBOL_RATE        7

#define DEFAULT_DVB_T_BANDWIDTH          8


typedef struct Scan_Context {
   int      carrier_count;
   double  *rf;
   int     *standard;
   void   **carrier_details;
} Scan_Context;

typedef struct L2_Context {
   L1_Context *demod;
   L1_Context *tuner;
   void       *specific;
} L2_Context;

typedef struct Si2165_Context {
  int         standard;
  double      FVCO;
  double      adc_clk;
  double      sys_clk;
  double      FE_clk;
  double      dvb_rate;
  double      digital_if_MHz;
  double      symbol_rate_MHz;
  int         bandwidth_MHz;
  int         ber_depth;
} Si2165_Context;

#ifdef RWTRACES
    //#warning "register-level traces activated (RWTRACES defined)"
  #ifdef   INDEXING_MODE_8_BITS
    #define L1_READ(ptr, register)      L1_ReadRegisterTrace8Bits  (ptr, #register,     register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_SIGNED)
    #define L1_WRITE(ptr, register, v ) L1_WriteRegisterTrace8Bits (ptr, #register, #v, register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_ALONE, v)
  #else
    #define L1_READ(ptr, register)      L1_ReadRegisterTrace  (ptr, #register,     register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_SIGNED)
    #define L1_WRITE(ptr, register, v ) L1_WriteRegisterTrace (ptr, #register, #v, register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_ALONE, v)
  #endif /* INDEXING_MODE_8_BITS  */
#else
  #ifdef   INDEXING_MODE_8_BITS
    #define L1_READ(ptr, register)      L1_ReadRegister8Bits  (ptr, register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_SIGNED)
    #define L1_WRITE(ptr, register, v ) L1_WriteRegister8Bits (ptr, register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_ALONE, v)
  #else
    #define L1_READ(ptr, register)      L1_ReadRegister  (ptr, register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_SIGNED)
    #define L1_WRITE(ptr, register, v ) L1_WriteRegister (ptr, register##_ADDRESS, register##_OFFSET, register##_NBBIT, register##_ALONE, v)
  #endif /* INDEXING_MODE_8_BITS  */
#endif /* RWTRACES */

 typedef struct DVB_T_Status {
   int		stream;
   int		fft_mode;
   int		guard_interval;
   int		constellation;
   int		code_rate_hp;
   int		code_rate_lp;
   int		hierarchy;
 } DVB_T_Status;

 typedef struct DVB_C_Status {
   int		constellation;
   int		spectral_inversion;
 } DVB_C_Status;
/**function			*/

static INT32 f_si2165_get_BER(struct nim_device *dev, UINT32 *vbber);


 /* i2c_passthru                   */
 #define    i2c_passthru_ADDRESS               1
 #define    i2c_passthru_OFFSET                0
 #define    i2c_passthru_NBBIT                 1
 #define    i2c_passthru_ALONE                 1
 #define    i2c_passthru_SIGNED                0
  #define           i2c_passthru_disabled                      0
  #define           i2c_passthru_enabled                       1
 /* i2c_addr_cap                   */
 #define    i2c_addr_cap_ADDRESS               2
 #define    i2c_addr_cap_OFFSET                0
 #define    i2c_addr_cap_NBBIT                 1
 #define    i2c_addr_cap_ALONE                 0
 #define    i2c_addr_cap_SIGNED                0
  #define           i2c_addr_cap_use_addr_pin                  0
  #define           i2c_addr_cap_use_stored_addr               1
 /* i2c_addrdet_dis                */
 #define    i2c_addrdet_dis_ADDRESS            2
 #define    i2c_addrdet_dis_OFFSET             1
 #define    i2c_addrdet_dis_NBBIT              1
 #define    i2c_addrdet_dis_ALONE              0
 #define    i2c_addrdet_dis_SIGNED             0
  #define           i2c_addrdet_dis_enabled                    0
  #define           i2c_addrdet_dis_disabled                   1
 /* test_vin                       */
 #define    test_vin_ADDRESS                   3
 #define    test_vin_OFFSET                    0
 #define    test_vin_NBBIT                     1
 #define    test_vin_ALONE                     0
 #define    test_vin_SIGNED                    0
  #define           test_vin_disable_test                      0
  #define           test_vin_enable_test                       1
 /* test_voh                       */
 #define    test_voh_ADDRESS                   3
 #define    test_voh_OFFSET                    1
 #define    test_voh_NBBIT                     1
 #define    test_voh_ALONE                     0
 #define    test_voh_SIGNED                    0
  #define           test_voh_disable_test                      0
  #define           test_voh_enable_drive_1                    1
 /* test_vol                       */
 #define    test_vol_ADDRESS                   3
 #define    test_vol_OFFSET                    2
 #define    test_vol_NBBIT                     1
 #define    test_vol_ALONE                     0
 #define    test_vol_SIGNED                    0
  #define           test_vol_disable_test                      0
  #define           test_vol_enable_drive_0                    1
 /* i2c_delay_off                  */
 #define    i2c_delay_off_ADDRESS              3
 #define    i2c_delay_off_OFFSET               3
 #define    i2c_delay_off_NBBIT                1
 #define    i2c_delay_off_ALONE                0
 #define    i2c_delay_off_SIGNED               0
  #define           i2c_delay_off_delay_enabled                0
  #define           i2c_delay_off_delay_bypassed               1
 /* scan_mode                      */
 #define    scan_mode_ADDRESS                  4
 #define    scan_mode_OFFSET                   0
 #define    scan_mode_NBBIT                    8
 #define    scan_mode_ALONE                    1
 #define    scan_mode_SIGNED                   0
  #define           scan_mode_mission_mode                     0
  #define           scan_mode_scan_compress                   92
  #define           scan_mode_scan_normal                     93
 /* i2c_addr                       */
 #define    i2c_addr_ADDRESS                  19
 #define    i2c_addr_OFFSET                    0
 #define    i2c_addr_NBBIT                     2
 #define    i2c_addr_ALONE                     1
 #define    i2c_addr_SIGNED                    0
 /* i2c_passthru_ovr               */
 #define    i2c_passthru_ovr_ADDRESS          20
 #define    i2c_passthru_ovr_OFFSET            0
 #define    i2c_passthru_ovr_NBBIT             1
 #define    i2c_passthru_ovr_ALONE             0
 #define    i2c_passthru_ovr_SIGNED            0
  #define           i2c_passthru_ovr_disable                   0
  #define           i2c_passthru_ovr_enable                    1
 /* i2c_addr_cap_ovr               */
 #define    i2c_addr_cap_ovr_ADDRESS          20
 #define    i2c_addr_cap_ovr_OFFSET            1
 #define    i2c_addr_cap_ovr_NBBIT             1
 #define    i2c_addr_cap_ovr_ALONE             0
 #define    i2c_addr_cap_ovr_SIGNED            0
  #define           i2c_addr_cap_ovr_use_addr_pin              0
  #define           i2c_addr_cap_ovr_use_stored_addr           1
 /* i2c_addrdet_dis_ovr            */
 #define    i2c_addrdet_dis_ovr_ADDRESS       20
 #define    i2c_addrdet_dis_ovr_OFFSET         2
 #define    i2c_addrdet_dis_ovr_NBBIT          1
 #define    i2c_addrdet_dis_ovr_ALONE          0
 #define    i2c_addrdet_dis_ovr_SIGNED         0
  #define           i2c_addrdet_dis_ovr_disable                0
  #define           i2c_addrdet_dis_ovr_enable                 1
 /* i2c_config_ovr                 */
 #define    i2c_config_ovr_ADDRESS            20
 #define    i2c_config_ovr_OFFSET              3
 #define    i2c_config_ovr_NBBIT               1
 #define    i2c_config_ovr_ALONE               0
 #define    i2c_config_ovr_SIGNED              0
  #define           i2c_config_ovr_disable                     0
  #define           i2c_config_ovr_enable                      1
 /* r_i2c_passthru                 */
 #define    r_i2c_passthru_ADDRESS            21
 #define    r_i2c_passthru_OFFSET              0
 #define    r_i2c_passthru_NBBIT               1
 #define    r_i2c_passthru_ALONE               0
 #define    r_i2c_passthru_SIGNED              0
  #define           r_i2c_passthru_buses_separate              0
  #define           r_i2c_passthru_buses_connected             1
 /* r_i2c_addr_cap                 */
 #define    r_i2c_addr_cap_ADDRESS            21
 #define    r_i2c_addr_cap_OFFSET              1
 #define    r_i2c_addr_cap_NBBIT               1
 #define    r_i2c_addr_cap_ALONE               0
 #define    r_i2c_addr_cap_SIGNED              0
  #define           r_i2c_addr_cap_use_addr_pin                0
  #define           r_i2c_addr_cap_use_stored_addr             1
 /* r_i2c_addrdet_dis              */
 #define    r_i2c_addrdet_dis_ADDRESS         21
 #define    r_i2c_addrdet_dis_OFFSET           2
 #define    r_i2c_addrdet_dis_NBBIT            1
 #define    r_i2c_addrdet_dis_ALONE            0
 #define    r_i2c_addrdet_dis_SIGNED           0
  #define           r_i2c_addrdet_dis_disabled                 0
  #define           r_i2c_addrdet_dis_enabled                  1
 /* revcode                        */
 #define    revcode_ADDRESS                   35
 #define    revcode_OFFSET                     0
 #define    revcode_NBBIT                      8
 #define    revcode_ALONE                      1
 #define    revcode_SIGNED                     0
  #define           revcode_rev_a                              0
  #define           revcode_rev_b                              1
  #define           revcode_rev_c                              2
 /* frontend_id                    */
 #define    frontend_id_ADDRESS               36
 #define    frontend_id_OFFSET                 0
 #define    frontend_id_NBBIT                 16
 #define    frontend_id_ALONE                  1
 #define    frontend_id_SIGNED                 0
 /* frontend_version               */
 #define    frontend_version_ADDRESS          38
 #define    frontend_version_OFFSET            0
 #define    frontend_version_NBBIT             8
 #define    frontend_version_ALONE             1
 #define    frontend_version_SIGNED            0
  #define           frontend_version_v1_0                     16
 /* demod_dvb_tc_id                */
 #define    demod_dvb_tc_id_ADDRESS           40
 #define    demod_dvb_tc_id_OFFSET             0
 #define    demod_dvb_tc_id_NBBIT             16
 #define    demod_dvb_tc_id_ALONE              1
 #define    demod_dvb_tc_id_SIGNED             0
 /* demod_dvb_tc_version           */
 #define    demod_dvb_tc_version_ADDRESS      42
 #define    demod_dvb_tc_version_OFFSET        0
 #define    demod_dvb_tc_version_NBBIT         8
 #define    demod_dvb_tc_version_ALONE         1
 #define    demod_dvb_tc_version_SIGNED        0
  #define           demod_dvb_tc_version_v1_0                 16
 /* equal_id                       */
 #define    equal_id_ADDRESS                  44
 #define    equal_id_OFFSET                    0
 #define    equal_id_NBBIT                    16
 #define    equal_id_ALONE                     1
 #define    equal_id_SIGNED                    0
 /* equal_version                  */
 #define    equal_version_ADDRESS             46
 #define    equal_version_OFFSET               0
 #define    equal_version_NBBIT                8
 #define    equal_version_ALONE                1
 #define    equal_version_SIGNED               0
  #define           equal_version_v1_0                        16
 /* equal_id_2                     */
 #define    equal_id_2_ADDRESS                48
 #define    equal_id_2_OFFSET                  0
 #define    equal_id_2_NBBIT                  16
 #define    equal_id_2_ALONE                   1
 #define    equal_id_2_SIGNED                  0
 /* equal_version_2                */
 #define    equal_version_2_ADDRESS           50
 #define    equal_version_2_OFFSET             0
 #define    equal_version_2_NBBIT              8
 #define    equal_version_2_ALONE              1
 #define    equal_version_2_SIGNED             0
  #define           equal_version_2_v1_0                      16
 /* synchro_dvb_t_id               */
 #define    synchro_dvb_t_id_ADDRESS          52
 #define    synchro_dvb_t_id_OFFSET            0
 #define    synchro_dvb_t_id_NBBIT            16
 #define    synchro_dvb_t_id_ALONE             1
 #define    synchro_dvb_t_id_SIGNED            0
 /* synchro_dvb_t_version          */
 #define    synchro_dvb_t_version_ADDRESS     56
 #define    synchro_dvb_t_version_OFFSET       0
 #define    synchro_dvb_t_version_NBBIT        8
 #define    synchro_dvb_t_version_ALONE        1
 #define    synchro_dvb_t_version_SIGNED       0
  #define           synchro_dvb_t_version_v1_0                16
 /* mcu_id                         */
 #define    mcu_id_ADDRESS                    60
 #define    mcu_id_OFFSET                      0
 #define    mcu_id_NBBIT                      16
 #define    mcu_id_ALONE                       1
 #define    mcu_id_SIGNED                      0
 /* mcu_version                    */
 #define    mcu_version_ADDRESS               64
 #define    mcu_version_OFFSET                 0
 #define    mcu_version_NBBIT                  8
 #define    mcu_version_ALONE                  1
 #define    mcu_version_SIGNED                 0
  #define           mcu_version_v1_0                          16
 /* fec_id                         */
 #define    fec_id_ADDRESS                    68
 #define    fec_id_OFFSET                      0
 #define    fec_id_NBBIT                      16
 #define    fec_id_ALONE                       1
 #define    fec_id_SIGNED                      0
 /* fec_version                    */
 #define    fec_version_ADDRESS               70
 #define    fec_version_OFFSET                 0
 #define    fec_version_NBBIT                  8
 #define    fec_version_ALONE                  1
 #define    fec_version_SIGNED                 0
  #define           fec_version_v1_0                          16
 /* dvb_tc_id                      */
 #define    dvb_tc_id_ADDRESS                 72
 #define    dvb_tc_id_OFFSET                   0
 #define    dvb_tc_id_NBBIT                   16
 #define    dvb_tc_id_ALONE                    1
 #define    dvb_tc_id_SIGNED                   0
 /* dvb_tc_version                 */
 #define    dvb_tc_version_ADDRESS            74
 #define    dvb_tc_version_OFFSET              0
 #define    dvb_tc_version_NBBIT               8
 #define    dvb_tc_version_ALONE               1
 #define    dvb_tc_version_SIGNED              0
  #define           dvb_tc_version_v0_0                        0
  #define           dvb_tc_version_v1_1                       17
 /* chip_init                      */
 #define    chip_init_ADDRESS                 80
 #define    chip_init_OFFSET                   0
 #define    chip_init_NBBIT                    1
 #define    chip_init_ALONE                    1
 #define    chip_init_SIGNED                   0
  #define           chip_init_func                             0
  #define           chip_init_init                             1
 /* init_done                      */
 #define    init_done_ADDRESS                 84
 #define    init_done_OFFSET                   0
 #define    init_done_NBBIT                    1
 #define    init_done_ALONE                    1
 #define    init_done_SIGNED                   0
  #define           init_done_pending                          0
  #define           init_done_completed                        1
 /* bist_error                     */
 #define    bist_error_ADDRESS                85
 #define    bist_error_OFFSET                  0
 #define    bist_error_NBBIT                   1
 #define    bist_error_ALONE                   0
 #define    bist_error_SIGNED                  0
  #define           bist_error_no_error                        0
  #define           bist_error_error                           1
 /* bist_repair_error              */
 #define    bist_repair_error_ADDRESS         85
 #define    bist_repair_error_OFFSET           1
 #define    bist_repair_error_NBBIT            1
 #define    bist_repair_error_ALONE            0
 #define    bist_repair_error_SIGNED           0
  #define           bist_repair_error_no_error                 0
  #define           bist_repair_error_repair_error             1
 /* bist_report                    */
 #define    bist_report_ADDRESS               85
 #define    bist_report_OFFSET                 2
 #define    bist_report_NBBIT                  1
 #define    bist_report_ALONE                  0
 #define    bist_report_SIGNED                 0
  #define           bist_report_fail                           0
  #define           bist_report_pass                           1
 /* bist_done_bus                  */
 #define    bist_done_bus_ADDRESS             86
 #define    bist_done_bus_OFFSET               0
 #define    bist_done_bus_NBBIT               10
 #define    bist_done_bus_ALONE                1
 #define    bist_done_bus_SIGNED               0
 /* bist_error_norpr               */
 #define    bist_error_norpr_ADDRESS          88
 #define    bist_error_norpr_OFFSET            0
 #define    bist_error_norpr_NBBIT            25
 #define    bist_error_norpr_ALONE             1
 #define    bist_error_norpr_SIGNED            0
 /* bist_error_rpr                 */
 #define    bist_error_rpr_ADDRESS            92
 #define    bist_error_rpr_OFFSET              0
 #define    bist_error_rpr_NBBIT              11
 #define    bist_error_rpr_ALONE               1
 #define    bist_error_rpr_SIGNED              0
 /* bist_repair_err                */
 #define    bist_repair_err_ADDRESS           94
 #define    bist_repair_err_OFFSET             0
 #define    bist_repair_err_NBBIT             11
 #define    bist_repair_err_ALONE              1
 #define    bist_repair_err_SIGNED             0
 /* bist_rom_misr                  */
 #define    bist_rom_misr_ADDRESS             96
 #define    bist_rom_misr_OFFSET               0
 #define    bist_rom_misr_NBBIT               32
 #define    bist_rom_misr_ALONE                1
 #define    bist_rom_misr_SIGNED               0
 /* bist_repair_data_lsb           */
 #define    bist_repair_data_lsb_ADDRESS     100
 #define    bist_repair_data_lsb_OFFSET        0
 #define    bist_repair_data_lsb_NBBIT        32
 #define    bist_repair_data_lsb_ALONE         1
 #define    bist_repair_data_lsb_SIGNED        0
 /* bist_repair_data_msb           */
 #define    bist_repair_data_msb_ADDRESS     104
 #define    bist_repair_data_msb_OFFSET        0
 #define    bist_repair_data_msb_NBBIT         9
 #define    bist_repair_data_msb_ALONE         1
 #define    bist_repair_data_msb_SIGNED        0
 /* bist_repair_addr               */
 #define    bist_repair_addr_ADDRESS         106
 #define    bist_repair_addr_OFFSET            0
 #define    bist_repair_addr_NBBIT             5
 #define    bist_repair_addr_ALONE             1
 #define    bist_repair_addr_SIGNED            0
  #define           bist_repair_addr_bdpram0                   0
  #define           bist_repair_addr_bdpram1                   1
  #define           bist_repair_addr_aram                      4
  #define           bist_repair_addr_symbol_deint              8
  #define           bist_repair_addr_cfd                      12
  #define           bist_repair_addr_dly_line1                13
  #define           bist_repair_addr_dly_line2                14
  #define           bist_repair_addr_pilots                   15
  #define           bist_repair_addr_bitreverse               16
  #define           bist_repair_addr_fft6                     17
  #define           bist_repair_addr_fft5                     18
 /* and_bist_fft5                  */
 #define    and_bist_fft5_ADDRESS            108
 #define    and_bist_fft5_OFFSET               0
 #define    and_bist_fft5_NBBIT               31
 #define    and_bist_fft5_ALONE                1
 #define    and_bist_fft5_SIGNED               0
 /* and_bist_fft6                  */
 #define    and_bist_fft6_ADDRESS            112
 #define    and_bist_fft6_OFFSET               0
 #define    and_bist_fft6_NBBIT               25
 #define    and_bist_fft6_ALONE                1
 #define    and_bist_fft6_SIGNED               0
 /* and_bist_fft1                  */
 #define    and_bist_fft1_ADDRESS            116
 #define    and_bist_fft1_OFFSET               0
 #define    and_bist_fft1_NBBIT                1
 #define    and_bist_fft1_ALONE                0
 #define    and_bist_fft1_SIGNED               0
 /* and_bist_fft2                  */
 #define    and_bist_fft2_ADDRESS            116
 #define    and_bist_fft2_OFFSET               1
 #define    and_bist_fft2_NBBIT                1
 #define    and_bist_fft2_ALONE                0
 #define    and_bist_fft2_SIGNED               0
 /* and_bist_fft3                  */
 #define    and_bist_fft3_ADDRESS            116
 #define    and_bist_fft3_OFFSET               2
 #define    and_bist_fft3_NBBIT                1
 #define    and_bist_fft3_ALONE                0
 #define    and_bist_fft3_SIGNED               0
 /* and_bist_fft4                  */
 #define    and_bist_fft4_ADDRESS            116
 #define    and_bist_fft4_OFFSET               3
 #define    and_bist_fft4_NBBIT                1
 #define    and_bist_fft4_ALONE                0
 #define    and_bist_fft4_SIGNED               0
 /* and_bist_cpe                   */
 #define    and_bist_cpe_ADDRESS             116
 #define    and_bist_cpe_OFFSET                4
 #define    and_bist_cpe_NBBIT                 1
 #define    and_bist_cpe_ALONE                 0
 #define    and_bist_cpe_SIGNED                0
 /* and_bist_deint0                */
 #define    and_bist_deint0_ADDRESS          116
 #define    and_bist_deint0_OFFSET             5
 #define    and_bist_deint0_NBBIT              1
 #define    and_bist_deint0_ALONE              0
 #define    and_bist_deint0_SIGNED             0
 /* and_bist_deint1                */
 #define    and_bist_deint1_ADDRESS          116
 #define    and_bist_deint1_OFFSET             6
 #define    and_bist_deint1_NBBIT              1
 #define    and_bist_deint1_ALONE              0
 #define    and_bist_deint1_SIGNED             0
 /* and_bist_deint2                */
 #define    and_bist_deint2_ADDRESS          116
 #define    and_bist_deint2_OFFSET             7
 #define    and_bist_deint2_NBBIT              1
 #define    and_bist_deint2_ALONE              0
 #define    and_bist_deint2_SIGNED             0
 /* and_bist_deint3                */
 #define    and_bist_deint3_ADDRESS          117
 #define    and_bist_deint3_OFFSET             0
 #define    and_bist_deint3_NBBIT              1
 #define    and_bist_deint3_ALONE              0
 #define    and_bist_deint3_SIGNED             0
 /* and_bist_deint4                */
 #define    and_bist_deint4_ADDRESS          117
 #define    and_bist_deint4_OFFSET             1
 #define    and_bist_deint4_NBBIT              1
 #define    and_bist_deint4_ALONE              0
 #define    and_bist_deint4_SIGNED             0
 /* and_bist_deint5                */
 #define    and_bist_deint5_ADDRESS          117
 #define    and_bist_deint5_OFFSET             2
 #define    and_bist_deint5_NBBIT              1
 #define    and_bist_deint5_ALONE              0
 #define    and_bist_deint5_SIGNED             0
 /* and_bist_deint                 */
 #define    and_bist_deint_ADDRESS           117
 #define    and_bist_deint_OFFSET              3
 #define    and_bist_deint_NBBIT               1
 #define    and_bist_deint_ALONE               0
 #define    and_bist_deint_SIGNED              0
 /* and_bist_rs0                   */
 #define    and_bist_rs0_ADDRESS             117
 #define    and_bist_rs0_OFFSET                4
 #define    and_bist_rs0_NBBIT                 1
 #define    and_bist_rs0_ALONE                 0
 #define    and_bist_rs0_SIGNED                0
 /* and_bist_rs1                   */
 #define    and_bist_rs1_ADDRESS             117
 #define    and_bist_rs1_OFFSET                5
 #define    and_bist_rs1_NBBIT                 1
 #define    and_bist_rs1_ALONE                 0
 #define    and_bist_rs1_SIGNED                0
 /* and_bist_vit0                  */
 #define    and_bist_vit0_ADDRESS            117
 #define    and_bist_vit0_OFFSET               6
 #define    and_bist_vit0_NBBIT                1
 #define    and_bist_vit0_ALONE                0
 #define    and_bist_vit0_SIGNED               0
 /* and_bist_vit1                  */
 #define    and_bist_vit1_ADDRESS            117
 #define    and_bist_vit1_OFFSET               7
 #define    and_bist_vit1_NBBIT                1
 #define    and_bist_vit1_ALONE                0
 #define    and_bist_vit1_SIGNED               0
 /* and_bist_vit2                  */
 #define    and_bist_vit2_ADDRESS            118
 #define    and_bist_vit2_OFFSET               0
 #define    and_bist_vit2_NBBIT                1
 #define    and_bist_vit2_ALONE                0
 #define    and_bist_vit2_SIGNED               0
 /* and_bist_cber                  */
 #define    and_bist_cber_ADDRESS            118
 #define    and_bist_cber_OFFSET               1
 #define    and_bist_cber_NBBIT                1
 #define    and_bist_cber_ALONE                0
 #define    and_bist_cber_SIGNED               0
 /* and_bist_gpif                  */
 #define    and_bist_gpif_ADDRESS            118
 #define    and_bist_gpif_OFFSET               2
 #define    and_bist_gpif_NBBIT                1
 #define    and_bist_gpif_ALONE                0
 #define    and_bist_gpif_SIGNED               0
 /* and_bist_rom                   */
 #define    and_bist_rom_ADDRESS             118
 #define    and_bist_rom_OFFSET                3
 #define    and_bist_rom_NBBIT                 1
 #define    and_bist_rom_ALONE                 0
 #define    and_bist_rom_SIGNED                0
 /* and_bist_corr0                 */
 #define    and_bist_corr0_ADDRESS           118
 #define    and_bist_corr0_OFFSET              4
 #define    and_bist_corr0_NBBIT               1
 #define    and_bist_corr0_ALONE               0
 #define    and_bist_corr0_SIGNED              0
 /* and_bist_corr1                 */
 #define    and_bist_corr1_ADDRESS           118
 #define    and_bist_corr1_OFFSET              5
 #define    and_bist_corr1_NBBIT               1
 #define    and_bist_corr1_ALONE               0
 #define    and_bist_corr1_SIGNED              0
 /* and_bist_iu0                   */
 #define    and_bist_iu0_ADDRESS             118
 #define    and_bist_iu0_OFFSET                6
 #define    and_bist_iu0_NBBIT                 1
 #define    and_bist_iu0_ALONE                 0
 #define    and_bist_iu0_SIGNED                0
 /* and_bist_iu1                   */
 #define    and_bist_iu1_ADDRESS             118
 #define    and_bist_iu1_OFFSET                7
 #define    and_bist_iu1_NBBIT                 1
 #define    and_bist_iu1_ALONE                 0
 #define    and_bist_iu1_SIGNED                0
 /* and_bist_itags                 */
 #define    and_bist_itags_ADDRESS           119
 #define    and_bist_itags_OFFSET              0
 #define    and_bist_itags_NBBIT               1
 #define    and_bist_itags_ALONE               0
 #define    and_bist_itags_SIGNED              0
 /* and_bist_data                  */
 #define    and_bist_data_ADDRESS            119
 #define    and_bist_data_OFFSET               1
 #define    and_bist_data_NBBIT                1
 #define    and_bist_data_ALONE                0
 #define    and_bist_data_SIGNED               0
 /* and_bist_br                    */
 #define    and_bist_br_ADDRESS              120
 #define    and_bist_br_OFFSET                 0
 #define    and_bist_br_NBBIT                 21
 #define    and_bist_br_ALONE                  1
 #define    and_bist_br_SIGNED                 0
 /* and_bist_dly                   */
 #define    and_bist_dly_ADDRESS             124
 #define    and_bist_dly_OFFSET                0
 #define    and_bist_dly_NBBIT                32
 #define    and_bist_dly_ALONE                 1
 #define    and_bist_dly_SIGNED                0
 /* and_bist_cfd                   */
 #define    and_bist_cfd_ADDRESS             128
 #define    and_bist_cfd_OFFSET                0
 #define    and_bist_cfd_NBBIT                13
 #define    and_bist_cfd_ALONE                 1
 #define    and_bist_cfd_SIGNED                0
 /* and_bist_pilot                 */
 #define    and_bist_pilot_ADDRESS           132
 #define    and_bist_pilot_OFFSET              0
 #define    and_bist_pilot_NBBIT              32
 #define    and_bist_pilot_ALONE               1
 #define    and_bist_pilot_SIGNED              0
 /* and_bist_symb_deint            */
 #define    and_bist_symb_deint_ADDRESS      136
 #define    and_bist_symb_deint_OFFSET         0
 #define    and_bist_symb_deint_NBBIT         25
 #define    and_bist_symb_deint_ALONE          1
 #define    and_bist_symb_deint_SIGNED         0
 /* and_bist_dpram                 */
 #define    and_bist_dpram_ADDRESS           140
 #define    and_bist_dpram_OFFSET              0
 #define    and_bist_dpram_NBBIT              32
 #define    and_bist_dpram_ALONE               1
 #define    and_bist_dpram_SIGNED              0
 /* and_bist_ahbram                */
 #define    and_bist_ahbram_ADDRESS          144
 #define    and_bist_ahbram_OFFSET             0
 #define    and_bist_ahbram_NBBIT             32
 #define    and_bist_ahbram_ALONE              1
 #define    and_bist_ahbram_SIGNED             0
 /* start_init                     */
 #define    start_init_ADDRESS               150
 #define    start_init_OFFSET                  0
 #define    start_init_NBBIT                   1
 #define    start_init_ALONE                   1
 #define    start_init_SIGNED                  0
  #define           start_init_reset                           0
  #define           start_init_run                             1
 /* bist_done_ovr                  */
 #define    bist_done_ovr_ADDRESS            151
 #define    bist_done_ovr_OFFSET               0
 #define    bist_done_ovr_NBBIT                1
 #define    bist_done_ovr_ALONE                0
 #define    bist_done_ovr_SIGNED               0
  #define           bist_done_ovr_func                         0
  #define           bist_done_ovr_forced                       1
 /* force_clk_bist                 */
 #define    force_clk_bist_ADDRESS           151
 #define    force_clk_bist_OFFSET              1
 #define    force_clk_bist_NBBIT               1
 #define    force_clk_bist_ALONE               0
 #define    force_clk_bist_SIGNED              0
  #define           force_clk_bist_func                        0
  #define           force_clk_bist_forced                      1
 /* pll_divl                       */
 #define    pll_divl_ADDRESS                 160
 #define    pll_divl_OFFSET                    0
 #define    pll_divl_NBBIT                     5
 #define    pll_divl_ALONE                     1
 #define    pll_divl_SIGNED                    0
 /* pll_divm                       */
 #define    pll_divm_ADDRESS                 161
 #define    pll_divm_OFFSET                    0
 #define    pll_divm_NBBIT                     5
 #define    pll_divm_ALONE                     1
 #define    pll_divm_SIGNED                    0
 /* pll_divn                       */
 #define    pll_divn_ADDRESS                 162
 #define    pll_divn_OFFSET                    0
 #define    pll_divn_NBBIT                     6
 #define    pll_divn_ALONE                     0
 #define    pll_divn_SIGNED                    0
 /* pll_divp                       */
 #define    pll_divp_ADDRESS                 162
 #define    pll_divp_OFFSET                    6
 #define    pll_divp_NBBIT                     1
 #define    pll_divp_ALONE                     0
 #define    pll_divp_SIGNED                    0
  #define           pll_divp_prescaler_4                       0
  #define           pll_divp_prescaler_1                       1
 /* pll_enable                     */
 #define    pll_enable_ADDRESS               162
 #define    pll_enable_OFFSET                  7
 #define    pll_enable_NBBIT                   1
 #define    pll_enable_ALONE                   0
 #define    pll_enable_SIGNED                  0
  #define           pll_enable_disable                         0
  #define           pll_enable_enable                          1
 /* pll_divr                       */
 #define    pll_divr_ADDRESS                 163
 #define    pll_divr_OFFSET                    0
 #define    pll_divr_NBBIT                     3
 #define    pll_divr_ALONE                     1
 #define    pll_divr_SIGNED                    0
 /* inv_clk_samp                   */
 #define    inv_clk_samp_ADDRESS             164
 #define    inv_clk_samp_OFFSET                0
 #define    inv_clk_samp_NBBIT                 1
 #define    inv_clk_samp_ALONE                 0
 #define    inv_clk_samp_SIGNED                0
  #define           inv_clk_samp_n                             0
  #define           inv_clk_samp_y                             1
 /* sel_clk_dsp                    */
 #define    sel_clk_dsp_ADDRESS              164
 #define    sel_clk_dsp_OFFSET                 1
 #define    sel_clk_dsp_NBBIT                  1
 #define    sel_clk_dsp_ALONE                  0
 #define    sel_clk_dsp_SIGNED                 0
  #define           sel_clk_dsp_clk_fsx4                       0
  #define           sel_clk_dsp_clk_samp                       1
 /* clock_backup                   */
 #define    clock_backup_ADDRESS             164
 #define    clock_backup_OFFSET                2
 #define    clock_backup_NBBIT                 1
 #define    clock_backup_ALONE                 0
 #define    clock_backup_SIGNED                0
  #define           clock_backup_normal                        0
  #define           clock_backup_backup                        1
 /* inv_clk_sdi                    */
 #define    inv_clk_sdi_ADDRESS              164
 #define    inv_clk_sdi_OFFSET                 3
 #define    inv_clk_sdi_NBBIT                  1
 #define    inv_clk_sdi_ALONE                  0
 #define    inv_clk_sdi_SIGNED                 0
  #define           inv_clk_sdi_n                              0
  #define           inv_clk_sdi_y                              1
 /* sdi_oversamp                   */
 #define    sdi_oversamp_ADDRESS             168
 #define    sdi_oversamp_OFFSET                0
 #define    sdi_oversamp_NBBIT                 3
 #define    sdi_oversamp_ALONE                 1
 #define    sdi_oversamp_SIGNED                0
 /* sdi_samp_low                   */
 #define    sdi_samp_low_ADDRESS             169
 #define    sdi_samp_low_OFFSET                0
 #define    sdi_samp_low_NBBIT                 3
 #define    sdi_samp_low_ALONE                 0
 #define    sdi_samp_low_SIGNED                0
 /* sdi_samp_high                  */
 #define    sdi_samp_high_ADDRESS            169
 #define    sdi_samp_high_OFFSET               4
 #define    sdi_samp_high_NBBIT                3
 #define    sdi_samp_high_ALONE                0
 #define    sdi_samp_high_SIGNED               0
 /* sdi_fsx4_low                   */
 #define    sdi_fsx4_low_ADDRESS             170
 #define    sdi_fsx4_low_OFFSET                0
 #define    sdi_fsx4_low_NBBIT                 3
 #define    sdi_fsx4_low_ALONE                 0
 #define    sdi_fsx4_low_SIGNED                0
 /* sdi_fsx4_high                  */
 #define    sdi_fsx4_high_ADDRESS            170
 #define    sdi_fsx4_high_OFFSET               4
 #define    sdi_fsx4_high_NBBIT                3
 #define    sdi_fsx4_high_ALONE                0
 #define    sdi_fsx4_high_SIGNED               0
 /* sdi_dsp_low                    */
 #define    sdi_dsp_low_ADDRESS              171
 #define    sdi_dsp_low_OFFSET                 0
 #define    sdi_dsp_low_NBBIT                  3
 #define    sdi_dsp_low_ALONE                  0
 #define    sdi_dsp_low_SIGNED                 0
 /* sdi_dsp_high                   */
 #define    sdi_dsp_high_ADDRESS             171
 #define    sdi_dsp_high_OFFSET                4
 #define    sdi_dsp_high_NBBIT                 3
 #define    sdi_dsp_high_ALONE                 0
 #define    sdi_dsp_high_SIGNED                0
 /* pll_ctrl_mode                  */
 #define    pll_ctrl_mode_ADDRESS            172
 #define    pll_ctrl_mode_OFFSET               0
 #define    pll_ctrl_mode_NBBIT                1
 #define    pll_ctrl_mode_ALONE                0
 #define    pll_ctrl_mode_SIGNED               0
  #define           pll_ctrl_mode_auto                         0
  #define           pll_ctrl_mode_manual                       1
 /* pll_pd                         */
 #define    pll_pd_ADDRESS                   172
 #define    pll_pd_OFFSET                      1
 #define    pll_pd_NBBIT                       1
 #define    pll_pd_ALONE                       0
 #define    pll_pd_SIGNED                      0
  #define           pll_pd_off                                 0
  #define           pll_pd_on                                  1
 /* pll_bypass                     */
 #define    pll_bypass_ADDRESS               172
 #define    pll_bypass_OFFSET                  2
 #define    pll_bypass_NBBIT                   1
 #define    pll_bypass_ALONE                   0
 #define    pll_bypass_SIGNED                  0
  #define           pll_bypass_n                               0
  #define           pll_bypass_y                               1
 /* ref_sel_clk                    */
 #define    ref_sel_clk_ADDRESS              172
 #define    ref_sel_clk_OFFSET                 3
 #define    ref_sel_clk_NBBIT                  1
 #define    ref_sel_clk_ALONE                  0
 #define    ref_sel_clk_SIGNED                 0
  #define           ref_sel_clk_dcxo                           0
  #define           ref_sel_clk_rssi                           1
 /* byp_sel_clk                    */
 #define    byp_sel_clk_ADDRESS              172
 #define    byp_sel_clk_OFFSET                 4
 #define    byp_sel_clk_NBBIT                  1
 #define    byp_sel_clk_ALONE                  0
 #define    byp_sel_clk_SIGNED                 0
  #define           byp_sel_clk_dcxo                           0
  #define           byp_sel_clk_rssi                           1
 /* adc_clk2_sel                   */
 #define    adc_clk2_sel_ADDRESS             172
 #define    adc_clk2_sel_OFFSET                5
 #define    adc_clk2_sel_NBBIT                 1
 #define    adc_clk2_sel_ALONE                 0
 #define    adc_clk2_sel_SIGNED                0
  #define           adc_clk2_sel_fs_clk2                       0
  #define           adc_clk2_sel_fs_adc                        1
 /* dcxo_ctrl_mode                 */
 #define    dcxo_ctrl_mode_ADDRESS           174
 #define    dcxo_ctrl_mode_OFFSET              0
 #define    dcxo_ctrl_mode_NBBIT               1
 #define    dcxo_ctrl_mode_ALONE               0
 #define    dcxo_ctrl_mode_SIGNED              0
  #define           dcxo_ctrl_mode_auto                        0
  #define           dcxo_ctrl_mode_manual                      1
 /* dcxo_pd                        */
 #define    dcxo_pd_ADDRESS                  174
 #define    dcxo_pd_OFFSET                     1
 #define    dcxo_pd_NBBIT                      1
 #define    dcxo_pd_ALONE                      0
 #define    dcxo_pd_SIGNED                     0
  #define           dcxo_pd_off                                0
  #define           dcxo_pd_on                                 1
 /* sdi_ctrl_mode                  */
 #define    sdi_ctrl_mode_ADDRESS            175
 #define    sdi_ctrl_mode_OFFSET               0
 #define    sdi_ctrl_mode_NBBIT                1
 #define    sdi_ctrl_mode_ALONE                0
 #define    sdi_ctrl_mode_SIGNED               0
  #define           sdi_ctrl_mode_auto                         0
  #define           sdi_ctrl_mode_manual                       1
 /* sdi_pd                         */
 #define    sdi_pd_ADDRESS                   175
 #define    sdi_pd_OFFSET                      1
 #define    sdi_pd_NBBIT                       1
 #define    sdi_pd_ALONE                       0
 #define    sdi_pd_SIGNED                      0
  #define           sdi_pd_off                                 0
  #define           sdi_pd_on                                  1
 /* analog_test                    */
 #define    analog_test_ADDRESS              176
 #define    analog_test_OFFSET                 0
 #define    analog_test_NBBIT                  2
 #define    analog_test_ALONE                  0
 #define    analog_test_SIGNED                 0
 /* analog_diag_disable            */
 #define    analog_diag_disable_ADDRESS      176
 #define    analog_diag_disable_OFFSET         2
 #define    analog_diag_disable_NBBIT          1
 #define    analog_diag_disable_ALONE          0
 #define    analog_diag_disable_SIGNED         0
  #define           analog_diag_disable_enable                 0
  #define           analog_diag_disable_disable                1
 /* dcxo_test_enable               */
 #define    dcxo_test_enable_ADDRESS         177
 #define    dcxo_test_enable_OFFSET            0
 #define    dcxo_test_enable_NBBIT             1
 #define    dcxo_test_enable_ALONE             0
 #define    dcxo_test_enable_SIGNED            0
  #define           dcxo_test_enable_n                         0
  #define           dcxo_test_enable_y                         1
 /* pll_test_enable                */
 #define    pll_test_enable_ADDRESS          177
 #define    pll_test_enable_OFFSET             1
 #define    pll_test_enable_NBBIT              1
 #define    pll_test_enable_ALONE              0
 #define    pll_test_enable_SIGNED             0
  #define           pll_test_enable_n                          0
  #define           pll_test_enable_y                          1
 /* rst_all                        */
 #define    rst_all_ADDRESS                  192
 #define    rst_all_OFFSET                     0
 #define    rst_all_NBBIT                      1
 #define    rst_all_ALONE                      1
 #define    rst_all_SIGNED                     0
  #define           rst_all_reset                              0
  #define           rst_all_run                                1
 /* lock_timeout                   */
 #define    lock_timeout_ADDRESS             196
 #define    lock_timeout_OFFSET                0
 #define    lock_timeout_NBBIT                26
 #define    lock_timeout_ALONE                 1
 #define    lock_timeout_SIGNED                0
 /* auto_reset                     */
 #define    auto_reset_ADDRESS               203
 #define    auto_reset_OFFSET                  0
 #define    auto_reset_NBBIT                   1
 #define    auto_reset_ALONE                   1
 #define    auto_reset_SIGNED                  0
  #define           auto_reset_off                             0
  #define           auto_reset_on                              1
 /* rst_frontend                   */
 #define    rst_frontend_ADDRESS             205
 #define    rst_frontend_OFFSET                0
 #define    rst_frontend_NBBIT                 1
 #define    rst_frontend_ALONE                 0
 #define    rst_frontend_SIGNED                0
  #define           rst_frontend_reset                         0
  #define           rst_frontend_run                           1
 /* rst_demod                      */
 #define    rst_demod_ADDRESS                205
 #define    rst_demod_OFFSET                   1
 #define    rst_demod_NBBIT                    1
 #define    rst_demod_ALONE                    0
 #define    rst_demod_SIGNED                   0
  #define           rst_demod_reset                            0
  #define           rst_demod_run                              1
 /* rst_equal                      */
 #define    rst_equal_ADDRESS                205
 #define    rst_equal_OFFSET                   2
 #define    rst_equal_NBBIT                    1
 #define    rst_equal_ALONE                    0
 #define    rst_equal_SIGNED                   0
  #define           rst_equal_reset                            0
  #define           rst_equal_run                              1
 /* rst_fec                        */
 #define    rst_fec_ADDRESS                  205
 #define    rst_fec_OFFSET                     3
 #define    rst_fec_NBBIT                      1
 #define    rst_fec_ALONE                      0
 #define    rst_fec_SIGNED                     0
  #define           rst_fec_reset                              0
  #define           rst_fec_run                                1
 /* rst_synchro                    */
 #define    rst_synchro_ADDRESS              205
 #define    rst_synchro_OFFSET                 4
 #define    rst_synchro_NBBIT                  1
 #define    rst_synchro_ALONE                  0
 #define    rst_synchro_SIGNED                 0
  #define           rst_synchro_reset                          0
  #define           rst_synchro_run                            1
 /* rst_dsp                        */
 #define    rst_dsp_ADDRESS                  205
 #define    rst_dsp_OFFSET                     5
 #define    rst_dsp_NBBIT                      1
 #define    rst_dsp_ALONE                      0
 #define    rst_dsp_SIGNED                     0
  #define           rst_dsp_reset                              0
  #define           rst_dsp_run                                1
 /* rst_sdi                        */
 #define    rst_sdi_ADDRESS                  205
 #define    rst_sdi_OFFSET                     6
 #define    rst_sdi_NBBIT                      1
 #define    rst_sdi_ALONE                      0
 #define    rst_sdi_SIGNED                     0
  #define           rst_sdi_reset                              0
  #define           rst_sdi_run                                1
 /* rst_mcm                        */
 #define    rst_mcm_ADDRESS                  207
 #define    rst_mcm_OFFSET                     0
 #define    rst_mcm_NBBIT                      1
 #define    rst_mcm_ALONE                      0
 #define    rst_mcm_SIGNED                     0
  #define           rst_mcm_reset                              0
  #define           rst_mcm_run                                1
 /* rst_mcm_slr                    */
 #define    rst_mcm_slr_ADDRESS              207
 #define    rst_mcm_slr_OFFSET                 1
 #define    rst_mcm_slr_NBBIT                  2
 #define    rst_mcm_slr_ALONE                  0
 #define    rst_mcm_slr_SIGNED                 0
  #define           rst_mcm_slr_fastest edges                  0
  #define           rst_mcm_slr_slowest edges                  1
  #define           rst_mcm_slr_moderate edges                 2
  #define           rst_mcm_slr_fast edges                     3
 /* lock_time                      */
 #define    lock_time_ADDRESS                208
 #define    lock_time_OFFSET                   0
 #define    lock_time_NBBIT                   26
 #define    lock_time_ALONE                    1
 #define    lock_time_SIGNED                   0
 /* adc_sampling_mode              */
 #define    adc_sampling_mode_ADDRESS        224
 #define    adc_sampling_mode_OFFSET           0
 #define    adc_sampling_mode_NBBIT            2
 #define    adc_sampling_mode_ALONE            1
 #define    adc_sampling_mode_SIGNED           0
  #define           adc_sampling_mode_if_ovr4                  0
  #define           adc_sampling_mode_if_ovr2                  1
  #define           adc_sampling_mode_zif_ovr4                 2
  #define           adc_sampling_mode_zif_ovr2                 3
 /* oversamp                       */
 #define    oversamp_ADDRESS                 228
 #define    oversamp_OFFSET                    0
 #define    oversamp_NBBIT                    30
 #define    oversamp_ALONE                     1
 #define    oversamp_SIGNED                    0
 /* if_freq_shift                  */
 #define    if_freq_shift_ADDRESS            232
 #define    if_freq_shift_OFFSET               0
 #define    if_freq_shift_NBBIT               29
 #define    if_freq_shift_ALONE                1
 #define    if_freq_shift_SIGNED               1
 /* standard                       */
 #define    standard_ADDRESS                 236
 #define    standard_OFFSET                    0
 #define    standard_NBBIT                     6
 #define    standard_ALONE                     1
 #define    standard_SIGNED                    0
  #define           standard_dvb_t                             1
  #define           standard_dvb_h                             2
  #define           standard_isdb_t                            3
  #define           standard_dvb_c                             5
 /* fft_mode                       */
 #define    fft_mode_ADDRESS                 240
 #define    fft_mode_OFFSET                    0
 #define    fft_mode_NBBIT                     4
 #define    fft_mode_ALONE                     1
 #define    fft_mode_SIGNED                    0
  #define           fft_mode_2k                               11
  #define           fft_mode_4k                               12
  #define           fft_mode_8k                               13
 /* guard_interval                 */
 #define    guard_interval_ADDRESS           244
 #define    guard_interval_OFFSET              0
 #define    guard_interval_NBBIT               3
 #define    guard_interval_ALONE               1
 #define    guard_interval_SIGNED              0
  #define           guard_interval_1_32                        1
  #define           guard_interval_1_16                        2
  #define           guard_interval_1_8                         3
  #define           guard_interval_1_4                         4
 /* constellation                  */
 #define    constellation_ADDRESS            248
 #define    constellation_OFFSET               0
 #define    constellation_NBBIT                6
 #define    constellation_ALONE                1
 #define    constellation_SIGNED               0
  #define           constellation_qpsk                         3
  #define           constellation_qam16                        7
  #define           constellation_qam32                        8
  #define           constellation_qam64                        9
  #define           constellation_qam128                      10
  #define           constellation_qam256                      11
 /* adc_format                     */
 #define    adc_format_ADDRESS               259
 #define    adc_format_OFFSET                  0
 #define    adc_format_NBBIT                   1
 #define    adc_format_ALONE                   1
 #define    adc_format_SIGNED                  0
  #define           adc_format_offset_binary                   0
  #define           adc_format_2s_complement                   1
 /* dsp_clock                      */
 #define    dsp_clock_ADDRESS                260
 #define    dsp_clock_OFFSET                   0
 #define    dsp_clock_NBBIT                    1
 #define    dsp_clock_ALONE                    1
 #define    dsp_clock_SIGNED                   0
  #define           dsp_clock_disable                          0
  #define           dsp_clock_enable                           1
 /* code_rate_hp                   */
 #define    code_rate_hp_ADDRESS             264
 #define    code_rate_hp_OFFSET                0
 #define    code_rate_hp_NBBIT                 4
 #define    code_rate_hp_ALONE                 1
 #define    code_rate_hp_SIGNED                0
  #define           code_rate_hp_1_2                           1
  #define           code_rate_hp_2_3                           2
  #define           code_rate_hp_3_4                           3
  #define           code_rate_hp_5_6                           5
  #define           code_rate_hp_7_8                           7
 /* code_rate_lp                   */
 #define    code_rate_lp_ADDRESS             268
 #define    code_rate_lp_OFFSET                0
 #define    code_rate_lp_NBBIT                 4
 #define    code_rate_lp_ALONE                 1
 #define    code_rate_lp_SIGNED                0
  #define           code_rate_lp_1_2                           1
  #define           code_rate_lp_2_3                           2
  #define           code_rate_lp_3_4                           3
  #define           code_rate_lp_5_6                           5
  #define           code_rate_lp_7_8                           7
 /* alarm                          */
 #define    alarm_ADDRESS                    274
 #define    alarm_OFFSET                       0
 #define    alarm_NBBIT                        8
 #define    alarm_ALONE                        1
 #define    alarm_SIGNED                       0
 /* chip_mode_epb                  */
 #define    chip_mode_epb_ADDRESS            278
 #define    chip_mode_epb_OFFSET               0
 #define    chip_mode_epb_NBBIT                6
 #define    chip_mode_epb_ALONE                1
 #define    chip_mode_epb_SIGNED               0
  #define           chip_mode_epb_off                          0
  #define           chip_mode_epb_pll_ext                     32
  #define           chip_mode_epb_pll_xtal                    33
  #define           chip_mode_epb_pll_rssi                    34
  #define           chip_mode_epb_sdi_ext                     44
  #define           chip_mode_epb_sdi_rssi                    46
  #define           chip_mode_epb_gpio_ext                    48
  #define           chip_mode_epb_gpio_xtal                   49
  #define           chip_mode_epb_gpio_rssi1                  50
  #define           chip_mode_epb_gpio_rssi2                  51
 /* bond_opt                       */
 #define    bond_opt_ADDRESS                 280
 #define    bond_opt_OFFSET                    0
 #define    bond_opt_NBBIT                     3
 #define    bond_opt_ALONE                     1
 #define    bond_opt_SIGNED                    0
  #define           bond_opt_mcm_dvb_c                         1
  #define           bond_opt_mcm_dvb_t                         2
  #define           bond_opt_mcm_dvb_tc                        3
  #define           bond_opt_dvb_c                             5
  #define           bond_opt_dvb_t                             6
  #define           bond_opt_dvb_tc                            7
 /* iq_adc_swap                    */
 #define    iq_adc_swap_ADDRESS              290
 #define    iq_adc_swap_OFFSET                 0
 #define    iq_adc_swap_NBBIT                  1
 #define    iq_adc_swap_ALONE                  1
 #define    iq_adc_swap_SIGNED                 0
  #define           iq_adc_swap_not_swapped                    0
  #define           iq_adc_swap_swapped                        1
 /* adc_ri8                        */
 #define    adc_ri8_ADDRESS                  291
 #define    adc_ri8_OFFSET                     0
 #define    adc_ri8_NBBIT                      8
 #define    adc_ri8_ALONE                      1
 #define    adc_ri8_SIGNED                     0
 /* ana_spare_rd                   */
 #define    ana_spare_rd_ADDRESS             293
 #define    ana_spare_rd_OFFSET                0
 #define    ana_spare_rd_NBBIT                 8
 #define    ana_spare_rd_ALONE                 1
 #define    ana_spare_rd_SIGNED                0
 /* adc_ctrl_mode                  */
 #define    adc_ctrl_mode_ADDRESS            296
 #define    adc_ctrl_mode_OFFSET               0
 #define    adc_ctrl_mode_NBBIT                1
 #define    adc_ctrl_mode_ALONE                0
 #define    adc_ctrl_mode_SIGNED               0
  #define           adc_ctrl_mode_auto                         0
  #define           adc_ctrl_mode_manual                       1
 /* adc_mode                       */
 #define    adc_mode_ADDRESS                 296
 #define    adc_mode_OFFSET                    1
 #define    adc_mode_NBBIT                     2
 #define    adc_mode_ALONE                     0
 #define    adc_mode_SIGNED                    0
  #define           adc_mode_test                              0
  #define           adc_mode_standby                           1
  #define           adc_mode_sleep                             2
  #define           adc_mode_pdown                             3
 /* adc_os                         */
 #define    adc_os_ADDRESS                   296
 #define    adc_os_OFFSET                      3
 #define    adc_os_NBBIT                       1
 #define    adc_os_ALONE                       0
 #define    adc_os_SIGNED                      0
  #define           adc_os_offset_binary                       0
  #define           adc_os_2s_complement                       1
 /* adc_ri0                        */
 #define    adc_ri0_ADDRESS                  297
 #define    adc_ri0_OFFSET                     0
 #define    adc_ri0_NBBIT                      8
 #define    adc_ri0_ALONE                      1
 #define    adc_ri0_SIGNED                     0
 /* adc_ri1                        */
 #define    adc_ri1_ADDRESS                  298
 #define    adc_ri1_OFFSET                     0
 #define    adc_ri1_NBBIT                      8
 #define    adc_ri1_ALONE                      1
 #define    adc_ri1_SIGNED                     0
 /* adc_ri2                        */
 #define    adc_ri2_ADDRESS                  299
 #define    adc_ri2_OFFSET                     0
 #define    adc_ri2_NBBIT                      8
 #define    adc_ri2_ALONE                      1
 #define    adc_ri2_SIGNED                     0
 /* adc_ri3                        */
 #define    adc_ri3_ADDRESS                  300
 #define    adc_ri3_OFFSET                     0
 #define    adc_ri3_NBBIT                      8
 #define    adc_ri3_ALONE                      1
 #define    adc_ri3_SIGNED                     0
 /* adc_ri4                        */
 #define    adc_ri4_ADDRESS                  301
 #define    adc_ri4_OFFSET                     0
 #define    adc_ri4_NBBIT                      8
 #define    adc_ri4_ALONE                      1
 #define    adc_ri4_SIGNED                     0
 /* adc_ri5                        */
 #define    adc_ri5_ADDRESS                  302
 #define    adc_ri5_OFFSET                     0
 #define    adc_ri5_NBBIT                      8
 #define    adc_ri5_ALONE                      1
 #define    adc_ri5_SIGNED                     0
 /* adc_ri6                        */
 #define    adc_ri6_ADDRESS                  303
 #define    adc_ri6_OFFSET                     0
 #define    adc_ri6_NBBIT                      8
 #define    adc_ri6_ALONE                      1
 #define    adc_ri6_SIGNED                     0
 /* dc_coeff                       */
 #define    dc_coeff_ADDRESS                 305
 #define    dc_coeff_OFFSET                    0
 #define    dc_coeff_NBBIT                     3
 #define    dc_coeff_ALONE                     0
 #define    dc_coeff_SIGNED                    0
 /* dc_bypass                      */
 #define    dc_bypass_ADDRESS                305
 #define    dc_bypass_OFFSET                   3
 #define    dc_bypass_NBBIT                    1
 #define    dc_bypass_ALONE                    0
 #define    dc_bypass_SIGNED                   0
  #define           dc_bypass_not_bypassed                     0
  #define           dc_bypass_bypassed                         1
 /* dc_freeze                      */
 #define    dc_freeze_ADDRESS                305
 #define    dc_freeze_OFFSET                   4
 #define    dc_freeze_NBBIT                    1
 #define    dc_freeze_ALONE                    0
 #define    dc_freeze_SIGNED                   0
  #define           dc_freeze_unfrozen                         0
  #define           dc_freeze_frozen                           1
 /* dc_offset_i                    */
 #define    dc_offset_i_ADDRESS              306
 #define    dc_offset_i_OFFSET                 0
 #define    dc_offset_i_NBBIT                  8
 #define    dc_offset_i_ALONE                  1
 #define    dc_offset_i_SIGNED                 1
 /* dc_offset_q                    */
 #define    dc_offset_q_ADDRESS              307
 #define    dc_offset_q_OFFSET                 0
 #define    dc_offset_q_NBBIT                  8
 #define    dc_offset_q_ALONE                  1
 #define    dc_offset_q_SIGNED                 1
 /* iq_freeze                      */
 #define    iq_freeze_ADDRESS                308
 #define    iq_freeze_OFFSET                   0
 #define    iq_freeze_NBBIT                    1
 #define    iq_freeze_ALONE                    1
 #define    iq_freeze_SIGNED                   0
  #define           iq_freeze_unfrozen                         0
  #define           iq_freeze_frozen                           1
 /* iq_kagc                        */
 #define    iq_kagc_ADDRESS                  309
 #define    iq_kagc_OFFSET                     0
 #define    iq_kagc_NBBIT                      3
 #define    iq_kagc_ALONE                      1
 #define    iq_kagc_SIGNED                     0
 /* q_gain_ext                     */
 #define    q_gain_ext_ADDRESS               310
 #define    q_gain_ext_OFFSET                  0
 #define    q_gain_ext_NBBIT                  10
 #define    q_gain_ext_ALONE                   1
 #define    q_gain_ext_SIGNED                  0
 /* q_gain                         */
 #define    q_gain_ADDRESS                   316
 #define    q_gain_OFFSET                      0
 #define    q_gain_NBBIT                      10
 #define    q_gain_ALONE                       1
 #define    q_gain_SIGNED                      0
 /* phase_freeze                   */
 #define    phase_freeze_ADDRESS             320
 #define    phase_freeze_OFFSET                0
 #define    phase_freeze_NBBIT                 1
 #define    phase_freeze_ALONE                 1
 #define    phase_freeze_SIGNED                0
  #define           phase_freeze_unfrozen                      0
  #define           phase_freeze_frozen                        1
 /* phase_kloop                    */
 #define    phase_kloop_ADDRESS              321
 #define    phase_kloop_OFFSET                 0
 #define    phase_kloop_NBBIT                  3
 #define    phase_kloop_ALONE                  1
 #define    phase_kloop_SIGNED                 0
 /* phi_cor                        */
 #define    phi_cor_ADDRESS                  324
 #define    phi_cor_OFFSET                     0
 #define    phi_cor_NBBIT                     10
 #define    phi_cor_ALONE                      1
 #define    phi_cor_SIGNED                     1
 /* agc_crestf_dbx8                */
 #define    agc_crestf_dbx8_ADDRESS          336
 #define    agc_crestf_dbx8_OFFSET             0
 #define    agc_crestf_dbx8_NBBIT              8
 #define    agc_crestf_dbx8_ALONE              1
 #define    agc_crestf_dbx8_SIGNED             0
 /* agc_alpha_acq                  */
 #define    agc_alpha_acq_ADDRESS            340
 #define    agc_alpha_acq_OFFSET               0
 #define    agc_alpha_acq_NBBIT                5
 #define    agc_alpha_acq_ALONE                1
 #define    agc_alpha_acq_SIGNED               0
 /* agc_alpha_loc                  */
 #define    agc_alpha_loc_ADDRESS            341
 #define    agc_alpha_loc_OFFSET               0
 #define    agc_alpha_loc_NBBIT                5
 #define    agc_alpha_loc_ALONE                1
 #define    agc_alpha_loc_SIGNED               0
 /* agc_dicho_rate                 */
 #define    agc_dicho_rate_ADDRESS           342
 #define    agc_dicho_rate_OFFSET              0
 #define    agc_dicho_rate_NBBIT               8
 #define    agc_dicho_rate_ALONE               1
 #define    agc_dicho_rate_SIGNED              0
 /* agc_acq_mode                   */
 #define    agc_acq_mode_ADDRESS             343
 #define    agc_acq_mode_OFFSET                0
 #define    agc_acq_mode_NBBIT                 1
 #define    agc_acq_mode_ALONE                 1
 #define    agc_acq_mode_SIGNED                0
  #define           agc_acq_mode_loop_mode                     0
  #define           agc_acq_mode_dicho_mode                    1
 /* agc_coarse2fine_thr            */
 #define    agc_coarse2fine_thr_ADDRESS      344
 #define    agc_coarse2fine_thr_OFFSET         0
 #define    agc_coarse2fine_thr_NBBIT          4
 #define    agc_coarse2fine_thr_ALONE          1
 #define    agc_coarse2fine_thr_SIGNED         0
 /* agc_fine2coarse_thr            */
 #define    agc_fine2coarse_thr_ADDRESS      345
 #define    agc_fine2coarse_thr_OFFSET         0
 #define    agc_fine2coarse_thr_NBBIT          4
 #define    agc_fine2coarse_thr_ALONE          1
 #define    agc_fine2coarse_thr_SIGNED         0
 /* agc_freeze_thr                 */
 #define    agc_freeze_thr_ADDRESS           346
 #define    agc_freeze_thr_OFFSET              0
 #define    agc_freeze_thr_NBBIT               4
 #define    agc_freeze_thr_ALONE               1
 #define    agc_freeze_thr_SIGNED              0
 /* agc_unfreeze_thr               */
 #define    agc_unfreeze_thr_ADDRESS         347
 #define    agc_unfreeze_thr_OFFSET            0
 #define    agc_unfreeze_thr_NBBIT             4
 #define    agc_unfreeze_thr_ALONE             1
 #define    agc_unfreeze_thr_SIGNED            0
 /* agc1_kacq                      */
 #define    agc1_kacq_ADDRESS                348
 #define    agc1_kacq_OFFSET                   0
 #define    agc1_kacq_NBBIT                    5
 #define    agc1_kacq_ALONE                    1
 #define    agc1_kacq_SIGNED                   0
 /* agc1_kloc                      */
 #define    agc1_kloc_ADDRESS                349
 #define    agc1_kloc_OFFSET                   0
 #define    agc1_kloc_NBBIT                    5
 #define    agc1_kloc_ALONE                    1
 #define    agc1_kloc_SIGNED                   0
 /* agc1_min                       */
 #define    agc1_min_ADDRESS                 350
 #define    agc1_min_OFFSET                    0
 #define    agc1_min_NBBIT                     8
 #define    agc1_min_ALONE                     1
 #define    agc1_min_SIGNED                    0
 /* agc1_max                       */
 #define    agc1_max_ADDRESS                 351
 #define    agc1_max_OFFSET                    0
 #define    agc1_max_NBBIT                     8
 #define    agc1_max_ALONE                     1
 #define    agc1_max_SIGNED                    0
 /* agc1_freeze                    */
 #define    agc1_freeze_ADDRESS              352
 #define    agc1_freeze_OFFSET                 0
 #define    agc1_freeze_NBBIT                  1
 #define    agc1_freeze_ALONE                  0
 #define    agc1_freeze_SIGNED                 0
  #define           agc1_freeze_unfrozen                       0
  #define           agc1_freeze_frozen                         1
 /* agc1_pola                      */
 #define    agc1_pola_ADDRESS                352
 #define    agc1_pola_OFFSET                   1
 #define    agc1_pola_NBBIT                    1
 #define    agc1_pola_ALONE                    0
 #define    agc1_pola_SIGNED                   0
  #define           agc1_pola_non_inverted                     0
  #define           agc1_pola_inverted                         1
 /* agc1_buftype                   */
 #define    agc1_buftype_ADDRESS             352
 #define    agc1_buftype_OFFSET                2
 #define    agc1_buftype_NBBIT                 1
 #define    agc1_buftype_ALONE                 0
 #define    agc1_buftype_SIGNED                0
  #define           agc1_buftype_push_pull                     0
  #define           agc1_buftype_open_drain                    1
 /* agc1_clkdiv                    */
 #define    agc1_clkdiv_ADDRESS              353
 #define    agc1_clkdiv_OFFSET                 0
 #define    agc1_clkdiv_NBBIT                  3
 #define    agc1_clkdiv_ALONE                  1
 #define    agc1_clkdiv_SIGNED                 0
 /* agc1_ext                       */
 #define    agc1_ext_ADDRESS                 356
 #define    agc1_ext_OFFSET                    0
 #define    agc1_ext_NBBIT                     8
 #define    agc1_ext_ALONE                     1
 #define    agc1_ext_SIGNED                    0
 /* agc1_cmd                       */
 #define    agc1_cmd_ADDRESS                 360
 #define    agc1_cmd_OFFSET                    0
 #define    agc1_cmd_NBBIT                     8
 #define    agc1_cmd_ALONE                     1
 #define    agc1_cmd_SIGNED                    0
 /* agc2_kacq                      */
 #define    agc2_kacq_ADDRESS                364
 #define    agc2_kacq_OFFSET                   0
 #define    agc2_kacq_NBBIT                    5
 #define    agc2_kacq_ALONE                    1
 #define    agc2_kacq_SIGNED                   0
 /* agc2_kloc                      */
 #define    agc2_kloc_ADDRESS                365
 #define    agc2_kloc_OFFSET                   0
 #define    agc2_kloc_NBBIT                    5
 #define    agc2_kloc_ALONE                    1
 #define    agc2_kloc_SIGNED                   0
 /* agc2_min                       */
 #define    agc2_min_ADDRESS                 366
 #define    agc2_min_OFFSET                    0
 #define    agc2_min_NBBIT                     8
 #define    agc2_min_ALONE                     1
 #define    agc2_min_SIGNED                    0
 /* agc2_max                       */
 #define    agc2_max_ADDRESS                 367
 #define    agc2_max_OFFSET                    0
 #define    agc2_max_NBBIT                     8
 #define    agc2_max_ALONE                     1
 #define    agc2_max_SIGNED                    0
 /* agc2_freeze                    */
 #define    agc2_freeze_ADDRESS              368
 #define    agc2_freeze_OFFSET                 0
 #define    agc2_freeze_NBBIT                  1
 #define    agc2_freeze_ALONE                  0
 #define    agc2_freeze_SIGNED                 0
  #define           agc2_freeze_unfrozen                       0
  #define           agc2_freeze_frozen                         1
 /* agc2_pola                      */
 #define    agc2_pola_ADDRESS                368
 #define    agc2_pola_OFFSET                   1
 #define    agc2_pola_NBBIT                    1
 #define    agc2_pola_ALONE                    0
 #define    agc2_pola_SIGNED                   0
  #define           agc2_pola_non_inverted                     0
  #define           agc2_pola_inverted                         1
 /* agc2_buftype                   */
 #define    agc2_buftype_ADDRESS             368
 #define    agc2_buftype_OFFSET                2
 #define    agc2_buftype_NBBIT                 1
 #define    agc2_buftype_ALONE                 0
 #define    agc2_buftype_SIGNED                0
  #define           agc2_buftype_push_pull                     0
  #define           agc2_buftype_open_drain                    1
 /* agc2_clkdiv                    */
 #define    agc2_clkdiv_ADDRESS              369
 #define    agc2_clkdiv_OFFSET                 0
 #define    agc2_clkdiv_NBBIT                  3
 #define    agc2_clkdiv_ALONE                  1
 #define    agc2_clkdiv_SIGNED                 0
 /* agc2_ext                       */
 #define    agc2_ext_ADDRESS                 372
 #define    agc2_ext_OFFSET                    0
 #define    agc2_ext_NBBIT                     8
 #define    agc2_ext_ALONE                     1
 #define    agc2_ext_SIGNED                    0
 /* agc2_cmd                       */
 #define    agc2_cmd_ADDRESS                 376
 #define    agc2_cmd_OFFSET                    0
 #define    agc2_cmd_NBBIT                     8
 #define    agc2_cmd_ALONE                     1
 #define    agc2_cmd_SIGNED                    0
 /* agc_pow_max                    */
 #define    agc_pow_max_ADDRESS              384
 #define    agc_pow_max_OFFSET                 0
 #define    agc_pow_max_NBBIT                  9
 #define    agc_pow_max_ALONE                  1
 #define    agc_pow_max_SIGNED                 0
 /* agc_pow_max_init               */
 #define    agc_pow_max_init_ADDRESS         388
 #define    agc_pow_max_init_OFFSET            0
 #define    agc_pow_max_init_NBBIT             1
 #define    agc_pow_max_init_ALONE             1
 #define    agc_pow_max_init_SIGNED            0
 /* agc_lock                       */
 #define    agc_lock_ADDRESS                 392
 #define    agc_lock_OFFSET                    0
 #define    agc_lock_NBBIT                     1
 #define    agc_lock_ALONE                     0
 #define    agc_lock_SIGNED                    0
  #define           agc_lock_unlocked                          0
  #define           agc_lock_locked                            1
 /* agc_freeze_int                 */
 #define    agc_freeze_int_ADDRESS           392
 #define    agc_freeze_int_OFFSET              1
 #define    agc_freeze_int_NBBIT               1
 #define    agc_freeze_int_ALONE               0
 #define    agc_freeze_int_SIGNED              0
  #define           agc_freeze_int_unfrozen                    0
  #define           agc_freeze_int_frozen                      1
 /* agc_if_tri                     */
 #define    agc_if_tri_ADDRESS               395
 #define    agc_if_tri_OFFSET                  0
 #define    agc_if_tri_NBBIT                   1
 #define    agc_if_tri_ALONE                   1
 #define    agc_if_tri_SIGNED                  0
  #define           agc_if_tri_normal                          0
  #define           agc_if_tri_tristate                        1
 /* agc_rf_tri                     */
 #define    agc_rf_tri_ADDRESS               397
 #define    agc_rf_tri_OFFSET                  0
 #define    agc_rf_tri_NBBIT                   1
 #define    agc_rf_tri_ALONE                   1
 #define    agc_rf_tri_SIGNED                  0
  #define           agc_rf_tri_normal                          0
  #define           agc_rf_tri_tristate                        1
 /* agc_if_slr                     */
 #define    agc_if_slr_ADDRESS               400
 #define    agc_if_slr_OFFSET                  0
 #define    agc_if_slr_NBBIT                   2
 #define    agc_if_slr_ALONE                   1
 #define    agc_if_slr_SIGNED                  0
  #define           agc_if_slr_fastest edges                   0
  #define           agc_if_slr_slowest edges                   1
  #define           agc_if_slr_moderate edges                  2
  #define           agc_if_slr_fast edges                      3
 /* agc_rf_slr                     */
 #define    agc_rf_slr_ADDRESS               402
 #define    agc_rf_slr_OFFSET                  0
 #define    agc_rf_slr_NBBIT                   2
 #define    agc_rf_slr_ALONE                   1
 #define    agc_rf_slr_SIGNED                  0
  #define           agc_rf_slr_fastest edges                   0
  #define           agc_rf_slr_slowest edges                   1
  #define           agc_rf_slr_moderate edges                  2
  #define           agc_rf_slr_fast edges                      3
 /* aaf_crestf_dbx8                */
 #define    aaf_crestf_dbx8_ADDRESS          416
 #define    aaf_crestf_dbx8_OFFSET             0
 #define    aaf_crestf_dbx8_NBBIT              8
 #define    aaf_crestf_dbx8_ALONE              1
 #define    aaf_crestf_dbx8_SIGNED             0
 /* aaf_alpha_acq                  */
 #define    aaf_alpha_acq_ADDRESS            420
 #define    aaf_alpha_acq_OFFSET               0
 #define    aaf_alpha_acq_NBBIT                5
 #define    aaf_alpha_acq_ALONE                1
 #define    aaf_alpha_acq_SIGNED               0
 /* aaf_alpha_loc                  */
 #define    aaf_alpha_loc_ADDRESS            421
 #define    aaf_alpha_loc_OFFSET               0
 #define    aaf_alpha_loc_NBBIT                5
 #define    aaf_alpha_loc_ALONE                1
 #define    aaf_alpha_loc_SIGNED               0
 /* aaf_agc_step                   */
 #define    aaf_agc_step_ADDRESS             422
 #define    aaf_agc_step_OFFSET                0
 #define    aaf_agc_step_NBBIT                 4
 #define    aaf_agc_step_ALONE                 1
 #define    aaf_agc_step_SIGNED                0
 /* aaf_agc_freeze                 */
 #define    aaf_agc_freeze_ADDRESS           423
 #define    aaf_agc_freeze_OFFSET              0
 #define    aaf_agc_freeze_NBBIT               1
 #define    aaf_agc_freeze_ALONE               0
 #define    aaf_agc_freeze_SIGNED              0
  #define           aaf_agc_freeze_frozen                      1
  #define           aaf_agc_freeze_unfrozen                    0
 /* aaf_update_sel                 */
 #define    aaf_update_sel_ADDRESS           423
 #define    aaf_update_sel_OFFSET              1
 #define    aaf_update_sel_NBBIT               1
 #define    aaf_update_sel_ALONE               0
 #define    aaf_update_sel_SIGNED              0
 /* aaf_coarse2fine_thr            */
 #define    aaf_coarse2fine_thr_ADDRESS      424
 #define    aaf_coarse2fine_thr_OFFSET         0
 #define    aaf_coarse2fine_thr_NBBIT          6
 #define    aaf_coarse2fine_thr_ALONE          1
 #define    aaf_coarse2fine_thr_SIGNED         0
 /* aaf_fine2coarse_thr            */
 #define    aaf_fine2coarse_thr_ADDRESS      425
 #define    aaf_fine2coarse_thr_OFFSET         0
 #define    aaf_fine2coarse_thr_NBBIT          6
 #define    aaf_fine2coarse_thr_ALONE          1
 #define    aaf_fine2coarse_thr_SIGNED         0
 /* aaf_freeze_thr                 */
 #define    aaf_freeze_thr_ADDRESS           426
 #define    aaf_freeze_thr_OFFSET              0
 #define    aaf_freeze_thr_NBBIT               6
 #define    aaf_freeze_thr_ALONE               1
 #define    aaf_freeze_thr_SIGNED              0
 /* aaf_unfreeze_thr               */
 #define    aaf_unfreeze_thr_ADDRESS         427
 #define    aaf_unfreeze_thr_OFFSET            0
 #define    aaf_unfreeze_thr_NBBIT             6
 #define    aaf_unfreeze_thr_ALONE             1
 #define    aaf_unfreeze_thr_SIGNED            0
 /* aaf_agc_ext                    */
 #define    aaf_agc_ext_ADDRESS              428
 #define    aaf_agc_ext_OFFSET                 0
 #define    aaf_agc_ext_NBBIT                  8
 #define    aaf_agc_ext_ALONE                  1
 #define    aaf_agc_ext_SIGNED                 0
 /* aaf_agc_cmd                    */
 #define    aaf_agc_cmd_ADDRESS              432
 #define    aaf_agc_cmd_OFFSET                 0
 #define    aaf_agc_cmd_NBBIT                  8
 #define    aaf_agc_cmd_ALONE                  1
 #define    aaf_agc_cmd_SIGNED                 0
 /* aaf_pow_fil                    */
 #define    aaf_pow_fil_ADDRESS              440
 #define    aaf_pow_fil_OFFSET                 0
 #define    aaf_pow_fil_NBBIT                 10
 #define    aaf_pow_fil_ALONE                  1
 #define    aaf_pow_fil_SIGNED                 0
 /* aaf_pow_max                    */
 #define    aaf_pow_max_ADDRESS              446
 #define    aaf_pow_max_OFFSET                 0
 #define    aaf_pow_max_NBBIT                  9
 #define    aaf_pow_max_ALONE                  1
 #define    aaf_pow_max_SIGNED                 0
 /* aaf_pow_max_init               */
 #define    aaf_pow_max_init_ADDRESS         448
 #define    aaf_pow_max_init_OFFSET            0
 #define    aaf_pow_max_init_NBBIT             1
 #define    aaf_pow_max_init_ALONE             1
 #define    aaf_pow_max_init_SIGNED            0
 /* aaf_lock                       */
 #define    aaf_lock_ADDRESS                 452
 #define    aaf_lock_OFFSET                    0
 #define    aaf_lock_NBBIT                     1
 #define    aaf_lock_ALONE                     0
 #define    aaf_lock_SIGNED                    0
  #define           aaf_lock_unlocked                          0
  #define           aaf_lock_locked                            1
 /* aaf_freeze_int                 */
 #define    aaf_freeze_int_ADDRESS           452
 #define    aaf_freeze_int_OFFSET              1
 #define    aaf_freeze_int_NBBIT               1
 #define    aaf_freeze_int_ALONE               0
 #define    aaf_freeze_int_SIGNED              0
  #define           aaf_freeze_int_unfrozen                    0
  #define           aaf_freeze_int_frozen                      1
 /* aci_crestf_dbx8                */
 #define    aci_crestf_dbx8_ADDRESS          456
 #define    aci_crestf_dbx8_OFFSET             0
 #define    aci_crestf_dbx8_NBBIT              8
 #define    aci_crestf_dbx8_ALONE              1
 #define    aci_crestf_dbx8_SIGNED             0
 /* aci_alpha_acq                  */
 #define    aci_alpha_acq_ADDRESS            460
 #define    aci_alpha_acq_OFFSET               0
 #define    aci_alpha_acq_NBBIT                5
 #define    aci_alpha_acq_ALONE                1
 #define    aci_alpha_acq_SIGNED               0
 /* aci_alpha_loc                  */
 #define    aci_alpha_loc_ADDRESS            461
 #define    aci_alpha_loc_OFFSET               0
 #define    aci_alpha_loc_NBBIT                5
 #define    aci_alpha_loc_ALONE                1
 #define    aci_alpha_loc_SIGNED               0
 /* aci_agc_step                   */
 #define    aci_agc_step_ADDRESS             462
 #define    aci_agc_step_OFFSET                0
 #define    aci_agc_step_NBBIT                 4
 #define    aci_agc_step_ALONE                 1
 #define    aci_agc_step_SIGNED                0
 /* aci_agc_freeze                 */
 #define    aci_agc_freeze_ADDRESS           463
 #define    aci_agc_freeze_OFFSET              0
 #define    aci_agc_freeze_NBBIT               1
 #define    aci_agc_freeze_ALONE               0
 #define    aci_agc_freeze_SIGNED              0
  #define           aci_agc_freeze_unfrozen                    0
  #define           aci_agc_freeze_frozen                      1
 /* aci_agc_update_sel             */
 #define    aci_agc_update_sel_ADDRESS       463
 #define    aci_agc_update_sel_OFFSET          1
 #define    aci_agc_update_sel_NBBIT           1
 #define    aci_agc_update_sel_ALONE           0
 #define    aci_agc_update_sel_SIGNED          0
  #define           aci_agc_update_sel_internal                0
  #define           aci_agc_update_sel_external                1
 /* aci_coarse2fine_thr            */
 #define    aci_coarse2fine_thr_ADDRESS      464
 #define    aci_coarse2fine_thr_OFFSET         0
 #define    aci_coarse2fine_thr_NBBIT          6
 #define    aci_coarse2fine_thr_ALONE          1
 #define    aci_coarse2fine_thr_SIGNED         0
 /* aci_fine2coarse_thr            */
 #define    aci_fine2coarse_thr_ADDRESS      465
 #define    aci_fine2coarse_thr_OFFSET         0
 #define    aci_fine2coarse_thr_NBBIT          6
 #define    aci_fine2coarse_thr_ALONE          1
 #define    aci_fine2coarse_thr_SIGNED         0
 /* aci_freeze_thr                 */
 #define    aci_freeze_thr_ADDRESS           466
 #define    aci_freeze_thr_OFFSET              0
 #define    aci_freeze_thr_NBBIT               6
 #define    aci_freeze_thr_ALONE               1
 #define    aci_freeze_thr_SIGNED              0
 /* aci_unfreeze_thr               */
 #define    aci_unfreeze_thr_ADDRESS         467
 #define    aci_unfreeze_thr_OFFSET            0
 #define    aci_unfreeze_thr_NBBIT             6
 #define    aci_unfreeze_thr_ALONE             1
 #define    aci_unfreeze_thr_SIGNED            0
 /* aci_agc_ext                    */
 #define    aci_agc_ext_ADDRESS              468
 #define    aci_agc_ext_OFFSET                 0
 #define    aci_agc_ext_NBBIT                  8
 #define    aci_agc_ext_ALONE                  1
 #define    aci_agc_ext_SIGNED                 0
 /* aci_agc_cmd                    */
 #define    aci_agc_cmd_ADDRESS              472
 #define    aci_agc_cmd_OFFSET                 0
 #define    aci_agc_cmd_NBBIT                  8
 #define    aci_agc_cmd_ALONE                  1
 #define    aci_agc_cmd_SIGNED                 0
 /* aci_pow_fil                    */
 #define    aci_pow_fil_ADDRESS              480
 #define    aci_pow_fil_OFFSET                 0
 #define    aci_pow_fil_NBBIT                 10
 #define    aci_pow_fil_ALONE                  1
 #define    aci_pow_fil_SIGNED                 0
 /* aci_pow_max                    */
 #define    aci_pow_max_ADDRESS              486
 #define    aci_pow_max_OFFSET                 0
 #define    aci_pow_max_NBBIT                  9
 #define    aci_pow_max_ALONE                  1
 #define    aci_pow_max_SIGNED                 0
 /* aci_pow_max_init               */
 #define    aci_pow_max_init_ADDRESS         488
 #define    aci_pow_max_init_OFFSET            0
 #define    aci_pow_max_init_NBBIT             1
 #define    aci_pow_max_init_ALONE             1
 #define    aci_pow_max_init_SIGNED            0
 /* aci_lock                       */
 #define    aci_lock_ADDRESS                 492
 #define    aci_lock_OFFSET                    0
 #define    aci_lock_NBBIT                     1
 #define    aci_lock_ALONE                     0
 #define    aci_lock_SIGNED                    0
  #define           aci_lock_unlocked                          0
  #define           aci_lock_locked                            1
 /* aci_freeze_int                 */
 #define    aci_freeze_int_ADDRESS           492
 #define    aci_freeze_int_OFFSET              1
 #define    aci_freeze_int_NBBIT               1
 #define    aci_freeze_int_ALONE               0
 #define    aci_freeze_int_SIGNED              0
  #define           aci_freeze_int_unfrozen                    0
  #define           aci_freeze_int_frozen                      1
 /* aaf_unfrz_cond                 */
 #define    aaf_unfrz_cond_ADDRESS           496
 #define    aaf_unfrz_cond_OFFSET              0
 #define    aaf_unfrz_cond_NBBIT               2
 #define    aaf_unfrz_cond_ALONE               0
 #define    aaf_unfrz_cond_SIGNED              0
  #define           aaf_unfrz_cond_disable                     0
  #define           aaf_unfrz_cond_reset                       1
  #define           aaf_unfrz_cond_agc_lock                    2
 /* aci_unfrz_cond                 */
 #define    aci_unfrz_cond_ADDRESS           496
 #define    aci_unfrz_cond_OFFSET              2
 #define    aci_unfrz_cond_NBBIT               2
 #define    aci_unfrz_cond_ALONE               0
 #define    aci_unfrz_cond_SIGNED              0
  #define           aci_unfrz_cond_disable                     0
  #define           aci_unfrz_cond_reset                       1
  #define           aci_unfrz_cond_agc_lock                    2
  #define           aci_unfrz_cond_aaf_lock                    3
 /* tim_ki_acq                     */
 #define    tim_ki_acq_ADDRESS               512
 #define    tim_ki_acq_OFFSET                  0
 #define    tim_ki_acq_NBBIT                   5
 #define    tim_ki_acq_ALONE                   1
 #define    tim_ki_acq_SIGNED                  1
 /* tim_kp_acq                     */
 #define    tim_kp_acq_ADDRESS               513
 #define    tim_kp_acq_OFFSET                  0
 #define    tim_kp_acq_NBBIT                   4
 #define    tim_kp_acq_ALONE                   1
 #define    tim_kp_acq_SIGNED                  1
 /* tim_ki_loc                     */
 #define    tim_ki_loc_ADDRESS               514
 #define    tim_ki_loc_OFFSET                  0
 #define    tim_ki_loc_NBBIT                   5
 #define    tim_ki_loc_ALONE                   1
 #define    tim_ki_loc_SIGNED                  1
 /* tim_kp_loc                     */
 #define    tim_kp_loc_ADDRESS               515
 #define    tim_kp_loc_OFFSET                  0
 #define    tim_kp_loc_NBBIT                   4
 #define    tim_kp_loc_ALONE                   1
 #define    tim_kp_loc_SIGNED                  1
 /* timing_corr_c                  */
 #define    timing_corr_c_ADDRESS            520
 #define    timing_corr_c_OFFSET               0
 #define    timing_corr_c_NBBIT               18
 #define    timing_corr_c_ALONE                1
 #define    timing_corr_c_SIGNED               1
 /* tim_update_period              */
 #define    tim_update_period_ADDRESS        525
 #define    tim_update_period_OFFSET           0
 #define    tim_update_period_NBBIT            2
 #define    tim_update_period_ALONE            1
 #define    tim_update_period_SIGNED           0
 /* range_baud_rate                */
 #define    range_baud_rate_ADDRESS          529
 #define    range_baud_rate_OFFSET             0
 #define    range_baud_rate_NBBIT              6
 #define    range_baud_rate_ALONE              1
 #define    range_baud_rate_SIGNED             0
 /* coarsetim_corr                 */
 #define    coarsetim_corr_ADDRESS           532
 #define    coarsetim_corr_OFFSET              0
 #define    coarsetim_corr_NBBIT              12
 #define    coarsetim_corr_ALONE               1
 #define    coarsetim_corr_SIGNED              1
 /* baud_rate_unfrz_cond           */
 #define    baud_rate_unfrz_cond_ADDRESS     537
 #define    baud_rate_unfrz_cond_OFFSET        0
 #define    baud_rate_unfrz_cond_NBBIT         2
 #define    baud_rate_unfrz_cond_ALONE         0
 #define    baud_rate_unfrz_cond_SIGNED        0
  #define           baud_rate_unfrz_cond_disable               0
  #define           baud_rate_unfrz_cond_agc_lock              1
  #define           baud_rate_unfrz_cond_all_agc_lock          2
 /* timing_unfrz_cond              */
 #define    timing_unfrz_cond_ADDRESS        537
 #define    timing_unfrz_cond_OFFSET           2
 #define    timing_unfrz_cond_NBBIT            2
 #define    timing_unfrz_cond_ALONE            0
 #define    timing_unfrz_cond_SIGNED           0
  #define           timing_unfrz_cond_disable                  0
  #define           timing_unfrz_cond_agc_lock                 1
  #define           timing_unfrz_cond_all_agc_lock             2
  #define           timing_unfrz_cond_baud_rate_lock           3
 /* tim_alpha_iir1                 */
 #define    tim_alpha_iir1_ADDRESS           540
 #define    tim_alpha_iir1_OFFSET              0
 #define    tim_alpha_iir1_NBBIT               3
 #define    tim_alpha_iir1_ALONE               0
 #define    tim_alpha_iir1_SIGNED              0
 /* tim_alpha_iir2                 */
 #define    tim_alpha_iir2_ADDRESS           540
 #define    tim_alpha_iir2_OFFSET              3
 #define    tim_alpha_iir2_NBBIT               3
 #define    tim_alpha_iir2_ALONE               0
 #define    tim_alpha_iir2_SIGNED              0
 /* tim_period_thr_1               */
 #define    tim_period_thr_1_ADDRESS         542
 #define    tim_period_thr_1_OFFSET            0
 #define    tim_period_thr_1_NBBIT             8
 #define    tim_period_thr_1_ALONE             1
 #define    tim_period_thr_1_SIGNED            0
 /* tim_period_thr_2               */
 #define    tim_period_thr_2_ADDRESS         543
 #define    tim_period_thr_2_OFFSET            0
 #define    tim_period_thr_2_NBBIT             8
 #define    tim_period_thr_2_ALONE             1
 #define    tim_period_thr_2_SIGNED            0
 /* step_baud_rate                 */
 #define    step_baud_rate_ADDRESS           544
 #define    step_baud_rate_OFFSET              0
 #define    step_baud_rate_NBBIT               4
 #define    step_baud_rate_ALONE               1
 #define    step_baud_rate_SIGNED              0
 /* tim_lock_thr                   */
 #define    tim_lock_thr_ADDRESS             546
 #define    tim_lock_thr_OFFSET                0
 #define    tim_lock_thr_NBBIT                 8
 #define    tim_lock_thr_ALONE                 1
 #define    tim_lock_thr_SIGNED                0
 /* reset_short_per                */
 #define    reset_short_per_ADDRESS          547
 #define    reset_short_per_OFFSET             0
 #define    reset_short_per_NBBIT              1
 #define    reset_short_per_ALONE              0
 #define    reset_short_per_SIGNED             0
  #define           reset_short_per_not_reset                  0
  #define           reset_short_per_reset                      1
 /* estim_bias                     */
 #define    estim_bias_ADDRESS               547
 #define    estim_bias_OFFSET                  1
 #define    estim_bias_NBBIT                   2
 #define    estim_bias_ALONE                   0
 #define    estim_bias_SIGNED                  0
 /* tim_nb_trans                   */
 #define    tim_nb_trans_ADDRESS             548
 #define    tim_nb_trans_OFFSET                0
 #define    tim_nb_trans_NBBIT                15
 #define    tim_nb_trans_ALONE                 1
 #define    tim_nb_trans_SIGNED                0
 /* tim_lock_crit                  */
 #define    tim_lock_crit_ADDRESS            550
 #define    tim_lock_crit_OFFSET               0
 #define    tim_lock_crit_NBBIT               15
 #define    tim_lock_crit_ALONE                1
 #define    tim_lock_crit_SIGNED               0
 /* sweep_init                     */
 #define    sweep_init_ADDRESS               560
 #define    sweep_init_OFFSET                  0
 #define    sweep_init_NBBIT                   8
 #define    sweep_init_ALONE                   1
 #define    sweep_init_SIGNED                  1
 /* sweep_range                    */
 #define    sweep_range_ADDRESS              561
 #define    sweep_range_OFFSET                 0
 #define    sweep_range_NBBIT                  7
 #define    sweep_range_ALONE                  1
 #define    sweep_range_SIGNED                 0
 /* sweep_step                     */
 #define    sweep_step_ADDRESS               562
 #define    sweep_step_OFFSET                  0
 #define    sweep_step_NBBIT                   6
 #define    sweep_step_ALONE                   1
 #define    sweep_step_SIGNED                  1
 /* freq_corr_c                    */
 #define    freq_corr_c_ADDRESS              564
 #define    freq_corr_c_OFFSET                 0
 #define    freq_corr_c_NBBIT                 16
 #define    freq_corr_c_ALONE                  1
 #define    freq_corr_c_SIGNED                 1
 /* kp_acq                         */
 #define    kp_acq_ADDRESS                   568
 #define    kp_acq_OFFSET                      0
 #define    kp_acq_NBBIT                       4
 #define    kp_acq_ALONE                       1
 #define    kp_acq_SIGNED                      1
 /* ki_acq                         */
 #define    ki_acq_ADDRESS                   569
 #define    ki_acq_OFFSET                      0
 #define    ki_acq_NBBIT                       5
 #define    ki_acq_ALONE                       1
 #define    ki_acq_SIGNED                      1
 /* kp_lock                        */
 #define    kp_lock_ADDRESS                  570
 #define    kp_lock_OFFSET                     0
 #define    kp_lock_NBBIT                      4
 #define    kp_lock_ALONE                      1
 #define    kp_lock_SIGNED                     1
 /* ki_lock                        */
 #define    ki_lock_ADDRESS                  571
 #define    ki_lock_OFFSET                     0
 #define    ki_lock_NBBIT                      5
 #define    ki_lock_ALONE                      1
 #define    ki_lock_SIGNED                     1
 /* carrier_acq_range              */
 #define    carrier_acq_range_ADDRESS        572
 #define    carrier_acq_range_OFFSET           0
 #define    carrier_acq_range_NBBIT            8
 #define    carrier_acq_range_ALONE            1
 #define    carrier_acq_range_SIGNED           0
 /* demod_lock_c                   */
 #define    demod_lock_c_ADDRESS             574
 #define    demod_lock_c_OFFSET                0
 #define    demod_lock_c_NBBIT                 1
 #define    demod_lock_c_ALONE                 1
 #define    demod_lock_c_SIGNED                0
  #define           demod_lock_c_unlocked                      0
  #define           demod_lock_c_locked                        1
 /* phase_cor_c                    */
 #define    phase_cor_c_ADDRESS              576
 #define    phase_cor_c_OFFSET                 0
 #define    phase_cor_c_NBBIT                 16
 #define    phase_cor_c_ALONE                  1
 #define    phase_cor_c_SIGNED                 1
 /* freq_sweep_frz_cond            */
 #define    freq_sweep_frz_cond_ADDRESS      583
 #define    freq_sweep_frz_cond_OFFSET         0
 #define    freq_sweep_frz_cond_NBBIT          1
 #define    freq_sweep_frz_cond_ALONE          0
 #define    freq_sweep_frz_cond_SIGNED         0
  #define           freq_sweep_frz_cond_disable                0
  #define           freq_sweep_frz_cond_agc_unlock             1
 /* freq_sweep_unfrz_cond          */
 #define    freq_sweep_unfrz_cond_ADDRESS    583
 #define    freq_sweep_unfrz_cond_OFFSET       1
 #define    freq_sweep_unfrz_cond_NBBIT        2
 #define    freq_sweep_unfrz_cond_ALONE        0
 #define    freq_sweep_unfrz_cond_SIGNED       0
  #define           freq_sweep_unfrz_cond_disable              0
  #define           freq_sweep_unfrz_cond_all_agc_lock         1
  #define           freq_sweep_unfrz_cond_baud_rate_lock       2
  #define           freq_sweep_unfrz_cond_cma_lock             3
 /* phase_unfrz_cond               */
 #define    phase_unfrz_cond_ADDRESS         583
 #define    phase_unfrz_cond_OFFSET            3
 #define    phase_unfrz_cond_NBBIT             2
 #define    phase_unfrz_cond_ALONE             0
 #define    phase_unfrz_cond_SIGNED            0
  #define           phase_unfrz_cond_disable                   0
  #define           phase_unfrz_cond_all_agc_lock              1
  #define           phase_unfrz_cond_baud_rate_lock            2
  #define           phase_unfrz_cond_cma_lock                  3
 /* nb_phase_lock_thr              */
 #define    nb_phase_lock_thr_ADDRESS        584
 #define    nb_phase_lock_thr_OFFSET           0
 #define    nb_phase_lock_thr_NBBIT            4
 #define    nb_phase_lock_thr_ALONE            1
 #define    nb_phase_lock_thr_SIGNED           0
 /* nb_phase_unlock_thr            */
 #define    nb_phase_unlock_thr_ADDRESS      585
 #define    nb_phase_unlock_thr_OFFSET         0
 #define    nb_phase_unlock_thr_NBBIT          4
 #define    nb_phase_unlock_thr_ALONE          1
 #define    nb_phase_unlock_thr_SIGNED         0
 /* sweep_pause_length             */
 #define    sweep_pause_length_ADDRESS       587
 #define    sweep_pause_length_OFFSET          0
 #define    sweep_pause_length_NBBIT           5
 #define    sweep_pause_length_ALONE           1
 #define    sweep_pause_length_SIGNED          0
 /* phase_lock_thr                 */
 #define    phase_lock_thr_ADDRESS           588
 #define    phase_lock_thr_OFFSET              0
 #define    phase_lock_thr_NBBIT              16
 #define    phase_lock_thr_ALONE               1
 #define    phase_lock_thr_SIGNED              0
 /* phase_lock_thr_o               */
 #define    phase_lock_thr_o_ADDRESS         590
 #define    phase_lock_thr_o_OFFSET            0
 #define    phase_lock_thr_o_NBBIT            16
 #define    phase_lock_thr_o_ALONE             1
 #define    phase_lock_thr_o_SIGNED            0
 /* demod_lock_thr                 */
 #define    demod_lock_thr_ADDRESS           592
 #define    demod_lock_thr_OFFSET              0
 #define    demod_lock_thr_NBBIT              16
 #define    demod_lock_thr_ALONE               1
 #define    demod_lock_thr_SIGNED              0
 /* demod_lock_thr_o               */
 #define    demod_lock_thr_o_ADDRESS         594
 #define    demod_lock_thr_o_OFFSET            0
 #define    demod_lock_thr_o_NBBIT            16
 #define    demod_lock_thr_o_ALONE             1
 #define    demod_lock_thr_o_SIGNED            0
 /* phase_lock_c                   */
 #define    phase_lock_c_ADDRESS             597
 #define    phase_lock_c_OFFSET                0
 #define    phase_lock_c_NBBIT                 1
 #define    phase_lock_c_ALONE                 1
 #define    phase_lock_c_SIGNED                0
  #define           phase_lock_c_unlocked                      0
  #define           phase_lock_c_locked                        1
 /* ffe_length                     */
 #define    ffe_length_ADDRESS               608
 #define    ffe_length_OFFSET                  0
 #define    ffe_length_NBBIT                   7
 #define    ffe_length_ALONE                   1
 #define    ffe_length_SIGNED                  0
 /* central_tap                    */
 #define    central_tap_ADDRESS              609
 #define    central_tap_OFFSET                 0
 #define    central_tap_NBBIT                  8
 #define    central_tap_ALONE                  1
 #define    central_tap_SIGNED                 0
 /* gain_cma                       */
 #define    gain_cma_ADDRESS                 612
 #define    gain_cma_OFFSET                    0
 #define    gain_cma_NBBIT                     4
 #define    gain_cma_ALONE                     0
 #define    gain_cma_SIGNED                    0
  #define           gain_cma_auto                              0
  #define           gain_cma_1                                 1
  #define           gain_cma_2                                 2
  #define           gain_cma_4                                 3
  #define           gain_cma_8                                 4
  #define           gain_cma_16                                5
  #define           gain_cma_32                                6
  #define           gain_cma_64                                7
  #define           gain_cma_128                               8
 /* gain_ddffe                     */
 #define    gain_ddffe_ADDRESS               612
 #define    gain_ddffe_OFFSET                  4
 #define    gain_ddffe_NBBIT                   4
 #define    gain_ddffe_ALONE                   0
 #define    gain_ddffe_SIGNED                  0
  #define           gain_ddffe_auto                            0
  #define           gain_ddffe_1                               1
  #define           gain_ddffe_2                               2
  #define           gain_ddffe_4                               3
  #define           gain_ddffe_8                               4
  #define           gain_ddffe_16                              5
  #define           gain_ddffe_32                              6
  #define           gain_ddffe_64                              7
  #define           gain_ddffe_128                             8
 /* gain_dddfe                     */
 #define    gain_dddfe_ADDRESS               613
 #define    gain_dddfe_OFFSET                  0
 #define    gain_dddfe_NBBIT                   4
 #define    gain_dddfe_ALONE                   1
 #define    gain_dddfe_SIGNED                  0
  #define           gain_dddfe_auto                            0
  #define           gain_dddfe_1                               1
  #define           gain_dddfe_2                               2
  #define           gain_dddfe_4                               3
  #define           gain_dddfe_8                               4
  #define           gain_dddfe_16                              5
  #define           gain_dddfe_32                              6
  #define           gain_dddfe_64                              7
  #define           gain_dddfe_128                             8
 /* gain_cma_o                     */
 #define    gain_cma_o_ADDRESS               614
 #define    gain_cma_o_OFFSET                  0
 #define    gain_cma_o_NBBIT                   4
 #define    gain_cma_o_ALONE                   0
 #define    gain_cma_o_SIGNED                  0
  #define           gain_cma_o_1                               0
  #define           gain_cma_o_2                               1
  #define           gain_cma_o_4                               2
  #define           gain_cma_o_8                               3
  #define           gain_cma_o_16                              4
  #define           gain_cma_o_32                              5
  #define           gain_cma_o_64                              6
  #define           gain_cma_o_128                             7
 /* gain_ddffe_o                   */
 #define    gain_ddffe_o_ADDRESS             614
 #define    gain_ddffe_o_OFFSET                4
 #define    gain_ddffe_o_NBBIT                 4
 #define    gain_ddffe_o_ALONE                 0
 #define    gain_ddffe_o_SIGNED                0
  #define           gain_ddffe_o_1                             0
  #define           gain_ddffe_o_2                             1
  #define           gain_ddffe_o_4                             2
  #define           gain_ddffe_o_8                             3
  #define           gain_ddffe_o_16                            4
  #define           gain_ddffe_o_32                            5
  #define           gain_ddffe_o_64                            6
  #define           gain_ddffe_o_128                           7
 /* gain_dddfe_o                   */
 #define    gain_dddfe_o_ADDRESS             615
 #define    gain_dddfe_o_OFFSET                0
 #define    gain_dddfe_o_NBBIT                 4
 #define    gain_dddfe_o_ALONE                 1
 #define    gain_dddfe_o_SIGNED                0
  #define           gain_dddfe_o_1                             0
  #define           gain_dddfe_o_2                             1
  #define           gain_dddfe_o_4                             2
  #define           gain_dddfe_o_8                             3
  #define           gain_dddfe_o_16                            4
  #define           gain_dddfe_o_32                            5
  #define           gain_dddfe_o_64                            6
  #define           gain_dddfe_o_128                           7
 /* status_equal                   */
 #define    status_equal_ADDRESS             616
 #define    status_equal_OFFSET                0
 #define    status_equal_NBBIT                 2
 #define    status_equal_ALONE                 1
 #define    status_equal_SIGNED                0
  #define           status_equal_init                          0
  #define           status_equal_cma                           1
  #define           status_equal_dd_ffe                        2
  #define           status_equal_dd_full                       3
 /* c_n                            */
 #define    c_n_ADDRESS                      620
 #define    c_n_OFFSET                         0
 #define    c_n_NBBIT                         24
 #define    c_n_ALONE                          1
 #define    c_n_SIGNED                         0
 /* equal_frz_cond                 */
 #define    equal_frz_cond_ADDRESS           626
 #define    equal_frz_cond_OFFSET              0
 #define    equal_frz_cond_NBBIT               1
 #define    equal_frz_cond_ALONE               0
 #define    equal_frz_cond_SIGNED              0
  #define           equal_frz_cond_disable                     0
  #define           equal_frz_cond_agc_unlock                  1
 /* equal_unfrz_cond               */
 #define    equal_unfrz_cond_ADDRESS         626
 #define    equal_unfrz_cond_OFFSET            1
 #define    equal_unfrz_cond_NBBIT             2
 #define    equal_unfrz_cond_ALONE             0
 #define    equal_unfrz_cond_SIGNED            0
  #define           equal_unfrz_cond_disable                   0
  #define           equal_unfrz_cond_all_agc_lock              1
  #define           equal_unfrz_cond_baud_rate_lock            2
 /* ref_point                      */
 #define    ref_point_ADDRESS                628
 #define    ref_point_OFFSET                   0
 #define    ref_point_NBBIT                    8
 #define    ref_point_ALONE                    1
 #define    ref_point_SIGNED                   0
 /* ref_point_o                    */
 #define    ref_point_o_ADDRESS              629
 #define    ref_point_o_OFFSET                 0
 #define    ref_point_o_NBBIT                  8
 #define    ref_point_o_ALONE                  1
 #define    ref_point_o_SIGNED                 0
 /* ref_cma                        */
 #define    ref_cma_ADDRESS                  630
 #define    ref_cma_OFFSET                     0
 #define    ref_cma_NBBIT                      8
 #define    ref_cma_ALONE                      1
 #define    ref_cma_SIGNED                     0
 /* ref_cma_o                      */
 #define    ref_cma_o_ADDRESS                631
 #define    ref_cma_o_OFFSET                   0
 #define    ref_cma_o_NBBIT                    8
 #define    ref_cma_o_ALONE                    1
 #define    ref_cma_o_SIGNED                   0
 /* auto_control                   */
 #define    auto_control_ADDRESS             632
 #define    auto_control_OFFSET                0
 #define    auto_control_NBBIT                 1
 #define    auto_control_ALONE                 0
 #define    auto_control_SIGNED                0
  #define           auto_control_off                           0
  #define           auto_control_on                            1
 /* auto_algo                      */
 #define    auto_algo_ADDRESS                632
 #define    auto_algo_OFFSET                   1
 #define    auto_algo_NBBIT                    1
 #define    auto_algo_ALONE                    0
 #define    auto_algo_SIGNED                   0
  #define           auto_algo_dfe_init                         0
  #define           auto_algo_dfe_freeze                       1
 /* init_ffe                       */
 #define    init_ffe_ADDRESS                 632
 #define    init_ffe_OFFSET                    2
 #define    init_ffe_NBBIT                     1
 #define    init_ffe_ALONE                     0
 #define    init_ffe_SIGNED                    0
  #define           init_ffe_off                               0
  #define           init_ffe_on                                1
 /* init_dfe                       */
 #define    init_dfe_ADDRESS                 632
 #define    init_dfe_OFFSET                    3
 #define    init_dfe_NBBIT                     1
 #define    init_dfe_ALONE                     0
 #define    init_dfe_SIGNED                    0
  #define           init_dfe_off                               0
  #define           init_dfe_on                                1
 /* freeze_ffe                     */
 #define    freeze_ffe_ADDRESS               632
 #define    freeze_ffe_OFFSET                  4
 #define    freeze_ffe_NBBIT                   1
 #define    freeze_ffe_ALONE                   0
 #define    freeze_ffe_SIGNED                  0
  #define           freeze_ffe_off                             0
  #define           freeze_ffe_on                              1
 /* freeze_dfe                     */
 #define    freeze_dfe_ADDRESS               632
 #define    freeze_dfe_OFFSET                  5
 #define    freeze_dfe_NBBIT                   1
 #define    freeze_dfe_ALONE                   0
 #define    freeze_dfe_SIGNED                  0
  #define           freeze_dfe_off                             0
  #define           freeze_dfe_on                              1
 /* cma_dd                         */
 #define    cma_dd_ADDRESS                   632
 #define    cma_dd_OFFSET                      6
 #define    cma_dd_NBBIT                       1
 #define    cma_dd_ALONE                       0
 #define    cma_dd_SIGNED                      0
  #define           cma_dd_cma                                 0
  #define           cma_dd_dd                                  1
 /* ctap_im_freeze                 */
 #define    ctap_im_freeze_ADDRESS           633
 #define    ctap_im_freeze_OFFSET              0
 #define    ctap_im_freeze_NBBIT               1
 #define    ctap_im_freeze_ALONE               0
 #define    ctap_im_freeze_SIGNED              0
  #define           ctap_im_freeze_unfrozen                    0
  #define           ctap_im_freeze_frozen                      1
 /* c_n_update                     */
 #define    c_n_update_ADDRESS               633
 #define    c_n_update_OFFSET                  1
 #define    c_n_update_NBBIT                   2
 #define    c_n_update_ALONE                   0
 #define    c_n_update_SIGNED                  0
  #define           c_n_update_256_symbols                     0
  #define           c_n_update_512_symbols                     1
  #define           c_n_update_1024_symbols                    2
  #define           c_n_update_2048_symbols                    3
 /* cma2dd_thr                     */
 #define    cma2dd_thr_ADDRESS               636
 #define    cma2dd_thr_OFFSET                  0
 #define    cma2dd_thr_NBBIT                  16
 #define    cma2dd_thr_ALONE                   1
 #define    cma2dd_thr_SIGNED                  0
 /* cma2dd_thr_o                   */
 #define    cma2dd_thr_o_ADDRESS             638
 #define    cma2dd_thr_o_OFFSET                0
 #define    cma2dd_thr_o_NBBIT                16
 #define    cma2dd_thr_o_ALONE                 1
 #define    cma2dd_thr_o_SIGNED                0
 /* dfe_thr                        */
 #define    dfe_thr_ADDRESS                  640
 #define    dfe_thr_OFFSET                     0
 #define    dfe_thr_NBBIT                     16
 #define    dfe_thr_ALONE                      1
 #define    dfe_thr_SIGNED                     0
 /* dfe_thr_o                      */
 #define    dfe_thr_o_ADDRESS                642
 #define    dfe_thr_o_OFFSET                   0
 #define    dfe_thr_o_NBBIT                   16
 #define    dfe_thr_o_ALONE                    1
 #define    dfe_thr_o_SIGNED                   0
 /* coef_index                     */
 #define    coef_index_ADDRESS               647
 #define    coef_index_OFFSET                  0
 #define    coef_index_NBBIT                   8
 #define    coef_index_ALONE                   1
 #define    coef_index_SIGNED                  0
 /* coef_iq                        */
 #define    coef_iq_ADDRESS                  652
 #define    coef_iq_OFFSET                     0
 #define    coef_iq_NBBIT                     32
 #define    coef_iq_ALONE                      1
 #define    coef_iq_SIGNED                     0
 /* symb_output                    */
 #define    symb_output_ADDRESS              657
 #define    symb_output_OFFSET                 0
 #define    symb_output_NBBIT                  2
 #define    symb_output_ALONE                  1
 #define    symb_output_SIGNED                 0
  #define           symb_output_equal_input                    0
  #define           symb_output_ffe_output                     1
  #define           symb_output_mulc_output                    2
  #define           symb_output_equal_output                   3
 /* symb_iq_2                      */
 #define    symb_iq_2_ADDRESS                660
 #define    symb_iq_2_OFFSET                   0
 #define    symb_iq_2_NBBIT                   32
 #define    symb_iq_2_ALONE                    1
 #define    symb_iq_2_SIGNED                   0
 /* sigma2_est                     */
 #define    sigma2_est_ADDRESS               676
 #define    sigma2_est_OFFSET                  0
 #define    sigma2_est_NBBIT                  24
 #define    sigma2_est_ALONE                   1
 #define    sigma2_est_SIGNED                  0
 /* latency                        */
 #define    latency_ADDRESS                  683
 #define    latency_OFFSET                     0
 #define    latency_NBBIT                      4
 #define    latency_ALONE                      1
 #define    latency_SIGNED                     0
 /* echo_shift                     */
 #define    echo_shift_ADDRESS               684
 #define    echo_shift_OFFSET                  0
 #define    echo_shift_NBBIT                  14
 #define    echo_shift_ALONE                   1
 #define    echo_shift_SIGNED                  1
 /* nb_erase_sat                   */
 #define    nb_erase_sat_ADDRESS             691
 #define    nb_erase_sat_OFFSET                0
 #define    nb_erase_sat_NBBIT                 7
 #define    nb_erase_sat_ALONE                 1
 #define    nb_erase_sat_SIGNED                0
 /* equal_power                    */
 #define    equal_power_ADDRESS              696
 #define    equal_power_OFFSET                 0
 #define    equal_power_NBBIT                 16
 #define    equal_power_ALONE                  1
 #define    equal_power_SIGNED                 0
 /* equal_sat                      */
 #define    equal_sat_ADDRESS                702
 #define    equal_sat_OFFSET                   0
 #define    equal_sat_NBBIT                   10
 #define    equal_sat_ALONE                    1
 #define    equal_sat_SIGNED                   0
 /* ref_signal_power               */
 #define    ref_signal_power_ADDRESS         704
 #define    ref_signal_power_OFFSET            0
 #define    ref_signal_power_NBBIT            14
 #define    ref_signal_power_ALONE             1
 #define    ref_signal_power_SIGNED            0
 /* signaling                      */
 #define    signaling_ADDRESS                708
 #define    signaling_OFFSET                   0
 #define    signaling_NBBIT                    1
 #define    signaling_ALONE                    1
 #define    signaling_SIGNED                   0
  #define           signaling_0                                0
  #define           signaling_1                                1
 /* signaling_conf                 */
 #define    signaling_conf_ADDRESS           712
 #define    signaling_conf_OFFSET              0
 #define    signaling_conf_NBBIT               8
 #define    signaling_conf_ALONE               1
 #define    signaling_conf_SIGNED              1
 /* synchro_sel                    */
 #define    synchro_sel_ADDRESS              717
 #define    synchro_sel_OFFSET                 0
 #define    synchro_sel_NBBIT                  3
 #define    synchro_sel_ALONE                  1
 #define    synchro_sel_SIGNED                 0
  #define           synchro_sel_rk                             0
  #define           synchro_sel_ck                             1
  #define           synchro_sel_hk                             2
  #define           synchro_sel_sigma2                         3
  #define           synchro_sel_cfd                            4
  #define           synchro_sel_rk_before_dly                  5
 /* sel_phase                      */
 #define    sel_phase_ADDRESS                718
 #define    sel_phase_OFFSET                   0
 #define    sel_phase_NBBIT                    1
 #define    sel_phase_ALONE                    0
 #define    sel_phase_SIGNED                   0
  #define           sel_phase_dsp                              0
  #define           sel_phase_manual                           1
 /* demap_rescale                  */
 #define    demap_rescale_ADDRESS            718
 #define    demap_rescale_OFFSET               2
 #define    demap_rescale_NBBIT                1
 #define    demap_rescale_ALONE                0
 #define    demap_rescale_SIGNED               0
  #define           demap_rescale_off                          0
  #define           demap_rescale_on                           1
 /* symb_iq                        */
 #define    symb_iq_ADDRESS                  720
 #define    symb_iq_OFFSET                     0
 #define    symb_iq_NBBIT                     16
 #define    symb_iq_ALONE                      1
 #define    symb_iq_SIGNED                     0
 /* symb_index                     */
 #define    symb_index_ADDRESS               724
 #define    symb_index_OFFSET                  0
 #define    symb_index_NBBIT                  13
 #define    symb_index_ALONE                   1
 #define    symb_index_SIGNED                  0
 /* conf_index                     */
 #define    conf_index_ADDRESS               726
 #define    conf_index_OFFSET                  0
 #define    conf_index_NBBIT                  13
 #define    conf_index_ALONE                   1
 #define    conf_index_SIGNED                  0
 /* start_synchro                  */
 #define    start_synchro_ADDRESS            736
 #define    start_synchro_OFFSET               0
 #define    start_synchro_NBBIT                1
 #define    start_synchro_ALONE                1
 #define    start_synchro_SIGNED               0
  #define           start_synchro_running                      0
  #define           start_synchro_start                        1
 /* req_stream                     */
 #define    req_stream_ADDRESS               740
 #define    req_stream_OFFSET                  0
 #define    req_stream_NBBIT                   1
 #define    req_stream_ALONE                   1
 #define    req_stream_SIGNED                  0
  #define           req_stream_hp                              0
  #define           req_stream_lp                              1
 /* automatic_synchro              */
 #define    automatic_synchro_ADDRESS        744
 #define    automatic_synchro_OFFSET           0
 #define    automatic_synchro_NBBIT            1
 #define    automatic_synchro_ALONE            1
 #define    automatic_synchro_SIGNED           0
  #define           automatic_synchro_on                       0
  #define           automatic_synchro_off                      1
 /* req_fft_mode                   */
 #define    req_fft_mode_ADDRESS             748
 #define    req_fft_mode_OFFSET                0
 #define    req_fft_mode_NBBIT                 4
 #define    req_fft_mode_ALONE                 1
 #define    req_fft_mode_SIGNED                0
  #define           req_fft_mode_2k                           11
  #define           req_fft_mode_4k                           12
  #define           req_fft_mode_8k                           13
 /* req_guard_int                  */
 #define    req_guard_int_ADDRESS            752
 #define    req_guard_int_OFFSET               0
 #define    req_guard_int_NBBIT                3
 #define    req_guard_int_ALONE                1
 #define    req_guard_int_SIGNED               0
  #define           req_guard_int_1_32                         1
  #define           req_guard_int_1_16                         2
  #define           req_guard_int_1_8                          3
  #define           req_guard_int_1_4                          4
 /* req_constellation              */
 #define    req_constellation_ADDRESS        756
 #define    req_constellation_OFFSET           0
 #define    req_constellation_NBBIT            6
 #define    req_constellation_ALONE            1
 #define    req_constellation_SIGNED           0
  #define           req_constellation_qpsk                     3
  #define           req_constellation_qam16                    7
  #define           req_constellation_qam64                    9
 /* req_rate_hp                    */
 #define    req_rate_hp_ADDRESS              760
 #define    req_rate_hp_OFFSET                 0
 #define    req_rate_hp_NBBIT                  4
 #define    req_rate_hp_ALONE                  1
 #define    req_rate_hp_SIGNED                 0
  #define           req_rate_hp_1_2                            1
  #define           req_rate_hp_2_3                            2
  #define           req_rate_hp_3_4                            3
  #define           req_rate_hp_5_6                            5
  #define           req_rate_hp_7_8                            7
 /* req_rate_lp                    */
 #define    req_rate_lp_ADDRESS              768
 #define    req_rate_lp_OFFSET                 0
 #define    req_rate_lp_NBBIT                  4
 #define    req_rate_lp_ALONE                  1
 #define    req_rate_lp_SIGNED                 0
  #define           req_rate_lp_1_2                            1
  #define           req_rate_lp_2_3                            2
  #define           req_rate_lp_3_4                            3
  #define           req_rate_lp_5_6                            5
  #define           req_rate_lp_7_8                            7
 /* req_hierarchy                  */
 #define    req_hierarchy_ADDRESS            772
 #define    req_hierarchy_OFFSET               0
 #define    req_hierarchy_NBBIT                3
 #define    req_hierarchy_ALONE                1
 #define    req_hierarchy_SIGNED               0
  #define           req_hierarchy_none                         1
  #define           req_hierarchy_alfa1                        2
  #define           req_hierarchy_alfa2                        3
  #define           req_hierarchy_alfa4                        5
 /* bandwidth                      */
 #define    bandwidth_ADDRESS                776
 #define    bandwidth_OFFSET                   0
 #define    bandwidth_NBBIT                   14
 #define    bandwidth_ALONE                    1
 #define    bandwidth_SIGNED                   0
 /* freq_sync_range                */
 #define    freq_sync_range_ADDRESS          780
 #define    freq_sync_range_OFFSET             0
 #define    freq_sync_range_NBBIT             12
 #define    freq_sync_range_ALONE              1
 #define    freq_sync_range_SIGNED             0
 /* cpe_req                        */
 #define    cpe_req_ADDRESS                  784
 #define    cpe_req_OFFSET                     0
 #define    cpe_req_NBBIT                      1
 #define    cpe_req_ALONE                      1
 #define    cpe_req_SIGNED                     0
  #define           cpe_req_off                                0
  #define           cpe_req_on                                 1
 /* doppler_activation             */
 #define    doppler_activation_ADDRESS       788
 #define    doppler_activation_OFFSET          0
 #define    doppler_activation_NBBIT           1
 #define    doppler_activation_ALONE           1
 #define    doppler_activation_SIGNED          0
  #define           doppler_activation_off                     0
  #define           doppler_activation_on                      1
 /* timing_sync_range              */
 #define    timing_sync_range_ADDRESS        792
 #define    timing_sync_range_OFFSET           0
 #define    timing_sync_range_NBBIT            8
 #define    timing_sync_range_ALONE            1
 #define    timing_sync_range_SIGNED           0
 /* impulsive_noise_remover        */
 #define    impulsive_noise_remover_ADDRESS   796
 #define    impulsive_noise_remover_OFFSET      0
 #define    impulsive_noise_remover_NBBIT       1
 #define    impulsive_noise_remover_ALONE       1
 #define    impulsive_noise_remover_SIGNED      0
  #define           impulsive_noise_remover_off                0
  #define           impulsive_noise_remover_on                 1
 /* check_signal_thres             */
 #define    check_signal_thres_ADDRESS       800
 #define    check_signal_thres_OFFSET          0
 #define    check_signal_thres_NBBIT           4
 #define    check_signal_thres_ALONE           1
 #define    check_signal_thres_SIGNED          0
 /* relock_on_per_thres            */
 #define    relock_on_per_thres_ADDRESS      804
 #define    relock_on_per_thres_OFFSET         0
 #define    relock_on_per_thres_NBBIT          5
 #define    relock_on_per_thres_ALONE          1
 #define    relock_on_per_thres_SIGNED         0
 /* stay_lock_ber_thres            */
 #define    stay_lock_ber_thres_ADDRESS      808
 #define    stay_lock_ber_thres_OFFSET         0
 #define    stay_lock_ber_thres_NBBIT          5
 #define    stay_lock_ber_thres_ALONE          1
 #define    stay_lock_ber_thres_SIGNED         0
 /* tuner_interface                */
 #define    tuner_interface_ADDRESS          812
 #define    tuner_interface_OFFSET             0
 #define    tuner_interface_NBBIT              1
 #define    tuner_interface_ALONE              1
 #define    tuner_interface_SIGNED             0
  #define           tuner_interface_if_mode                    0
  #define           tuner_interface_zif_mode                   1
 /* zif_cluster_bandwidth          */
 #define    zif_cluster_bandwidth_ADDRESS    816
 #define    zif_cluster_bandwidth_OFFSET       0
 #define    zif_cluster_bandwidth_NBBIT        8
 #define    zif_cluster_bandwidth_ALONE        1
 #define    zif_cluster_bandwidth_SIGNED       0
 /* doppler_synchro_sel            */
 #define    doppler_synchro_sel_ADDRESS      817
 #define    doppler_synchro_sel_OFFSET         0
 #define    doppler_synchro_sel_NBBIT          1
 #define    doppler_synchro_sel_ALONE          1
 #define    doppler_synchro_sel_SIGNED         0
  #define           doppler_synchro_sel_fast                   0
  #define           doppler_synchro_sel_slow                   1
 /* freq_bw_acq                    */
 #define    freq_bw_acq_ADDRESS              820
 #define    freq_bw_acq_OFFSET                 0
 #define    freq_bw_acq_NBBIT                  4
 #define    freq_bw_acq_ALONE                  1
 #define    freq_bw_acq_SIGNED                 0
 /* freq_bw_track                  */
 #define    freq_bw_track_ADDRESS            822
 #define    freq_bw_track_OFFSET               0
 #define    freq_bw_track_NBBIT                4
 #define    freq_bw_track_ALONE                1
 #define    freq_bw_track_SIGNED               0
 /* timing_bw_acq                  */
 #define    timing_bw_acq_ADDRESS            824
 #define    timing_bw_acq_OFFSET               0
 #define    timing_bw_acq_NBBIT                4
 #define    timing_bw_acq_ALONE                1
 #define    timing_bw_acq_SIGNED               0
 /* timing_bw_track                */
 #define    timing_bw_track_ADDRESS          826
 #define    timing_bw_track_OFFSET             0
 #define    timing_bw_track_NBBIT              4
 #define    timing_bw_track_ALONE              1
 #define    timing_bw_track_SIGNED             0
 /* boot_done                      */
 #define    boot_done_ADDRESS                833
 #define    boot_done_OFFSET                   0
 #define    boot_done_NBBIT                    1
 #define    boot_done_ALONE                    0
 #define    boot_done_SIGNED                   0
  #define           boot_done_in_progress                      0
  #define           boot_done_done                             1
 /* rst_wdog_error                 */
 #define    rst_wdog_error_ADDRESS           833
 #define    rst_wdog_error_OFFSET              1
 #define    rst_wdog_error_NBBIT               1
 #define    rst_wdog_error_ALONE               0
 #define    rst_wdog_error_SIGNED              0
  #define           rst_wdog_error_run                         0
  #define           rst_wdog_error_reset                       1
 /* wdog_error                     */
 #define    wdog_error_ADDRESS               833
 #define    wdog_error_OFFSET                  2
 #define    wdog_error_NBBIT                   1
 #define    wdog_error_ALONE                   0
 #define    wdog_error_SIGNED                  0
  #define           wdog_error_no_error                        0
  #define           wdog_error_error                           1
 /* patch_version                  */
 #define    patch_version_ADDRESS            836
 #define    patch_version_OFFSET               0
 #define    patch_version_NBBIT                8
 #define    patch_version_ALONE                1
 #define    patch_version_SIGNED               0
 /* addr_jump                      */
 #define    addr_jump_ADDRESS                840
 #define    addr_jump_OFFSET                   0
 #define    addr_jump_NBBIT                   32
 #define    addr_jump_ALONE                    1
 #define    addr_jump_SIGNED                   0
 /* tbd_a                          */
 #define    tbd_a_ADDRESS                    844
 #define    tbd_a_OFFSET                       0
 #define    tbd_a_NBBIT                       16
 #define    tbd_a_ALONE                        1
 #define    tbd_a_SIGNED                       0
 /* tbd_b                          */
 #define    tbd_b_ADDRESS                    848
 #define    tbd_b_OFFSET                       0
 #define    tbd_b_NBBIT                       16
 #define    tbd_b_ALONE                        1
 #define    tbd_b_SIGNED                       0
 /* it_switch                      */
 #define    it_switch_ADDRESS                852
 #define    it_switch_OFFSET                   0
 #define    it_switch_NBBIT                    1
 #define    it_switch_ALONE                    1
 #define    it_switch_SIGNED                   0
  #define           it_switch_from_timer                       0
  #define           it_switch_from_dma                         1
 /* firmware_ctrl                  */
 #define    firmware_ctrl_ADDRESS            856
 #define    firmware_ctrl_OFFSET               0
 #define    firmware_ctrl_NBBIT               32
 #define    firmware_ctrl_ALONE                1
 #define    firmware_ctrl_SIGNED               0
 /* en_rst_error                   */
 #define    en_rst_error_ADDRESS             860
 #define    en_rst_error_OFFSET                0
 #define    en_rst_error_NBBIT                 1
 #define    en_rst_error_ALONE                 0
 #define    en_rst_error_SIGNED                0
  #define           en_rst_error_no_reset_on_errorn            0
  #define           en_rst_error_reset_on_errorn               1
 /* errorn                         */
 #define    errorn_ADDRESS                   860
 #define    errorn_OFFSET                      1
 #define    errorn_NBBIT                       1
 #define    errorn_ALONE                       0
 #define    errorn_SIGNED                      0
  #define           errorn_error_state                         0
  #define           errorn_no_error                            1
 /* trap_type                      */
 #define    trap_type_ADDRESS                862
 #define    trap_type_OFFSET                   0
 #define    trap_type_NBBIT                    8
 #define    trap_type_ALONE                    1
 #define    trap_type_SIGNED                   0
 /* program_counter                */
 #define    program_counter_ADDRESS          864
 #define    program_counter_OFFSET             0
 #define    program_counter_NBBIT             32
 #define    program_counter_ALONE              1
 #define    program_counter_SIGNED             0
 /* dcom_control_byte              */
 #define    dcom_control_byte_ADDRESS        868
 #define    dcom_control_byte_OFFSET           0
 #define    dcom_control_byte_NBBIT           32
 #define    dcom_control_byte_ALONE            1
 #define    dcom_control_byte_SIGNED           0
 /* dcom_addr                      */
 #define    dcom_addr_ADDRESS                872
 #define    dcom_addr_OFFSET                   0
 #define    dcom_addr_NBBIT                   32
 #define    dcom_addr_ALONE                    1
 #define    dcom_addr_SIGNED                   0
 /* dcom_data                      */
 #define    dcom_data_ADDRESS                876
 #define    dcom_data_OFFSET                   0
 #define    dcom_data_NBBIT                   32
 #define    dcom_data_ALONE                    1
 #define    dcom_data_SIGNED                   0
 /* firmware_id                    */
 #define    firmware_id_ADDRESS              880
 #define    firmware_id_OFFSET                 0
 #define    firmware_id_NBBIT                 16
 #define    firmware_id_ALONE                  1
 #define    firmware_id_SIGNED                 0
 /* firmware_version               */
 #define    firmware_version_ADDRESS         884
 #define    firmware_version_OFFSET            0
 #define    firmware_version_NBBIT             8
 #define    firmware_version_ALONE             1
 #define    firmware_version_SIGNED            0
  #define           firmware_version_v0_0                      0
  #define           firmware_version_v0_1                      1
  #define           firmware_version_v0_2                      2
  #define           firmware_version_v0_3                      3
  #define           firmware_version_v0_4                      4
  #define           firmware_version_v0_5                      5
  #define           firmware_version_v0_6                      6
  #define           firmware_version_v0_7                      7
  #define           firmware_version_v0_8                      8
  #define           firmware_version_v0_9                      9
  #define           firmware_version_v0_10                    10
  #define           firmware_version_v0_11                    11
  #define           firmware_version_v0_12                    12
  #define           firmware_version_v0_13                    13
  #define           firmware_version_v0_14                    14
  #define           firmware_version_v0_15                    15
  #define           firmware_version_v1_0                     16
  #define           firmware_version_v1_1                     17
  #define           firmware_version_v1_2                     18
  #define           firmware_version_v1_3                     19
  #define           firmware_version_v1_4                     20
  #define           firmware_version_v1_5                     21
  #define           firmware_version_v1_6                     22
  #define           firmware_version_v1_7                     23
  #define           firmware_version_v1_8                     24
  #define           firmware_version_v1_9                     25
  #define           firmware_version_v1_10                    26
  #define           firmware_version_v1_11                    27
  #define           firmware_version_v1_12                    28
  #define           firmware_version_v1_13                    29
  #define           firmware_version_v1_14                    30
  #define           firmware_version_v1_15                    31
  #define           firmware_version_v2_0                     32
  #define           firmware_version_v2_1                     33
  #define           firmware_version_v2_2                     34
  #define           firmware_version_v2_3                     35
  #define           firmware_version_v2_4                     36
  #define           firmware_version_v2_5                     37
  #define           firmware_version_v2_6                     38
  #define           firmware_version_v2_7                     39
  #define           firmware_version_v2_8                     40
  #define           firmware_version_v2_9                     41
  #define           firmware_version_v2_10                    42
  #define           firmware_version_v2_11                    43
  #define           firmware_version_v2_12                    44
  #define           firmware_version_v2_13                    45
  #define           firmware_version_v2_14                    46
  #define           firmware_version_v2_15                    47
 /* rst_crc                        */
 #define    rst_crc_ADDRESS                  889
 #define    rst_crc_OFFSET                     0
 #define    rst_crc_NBBIT                      1
 #define    rst_crc_ALONE                      1
 #define    rst_crc_SIGNED                     0
  #define           rst_crc_run                                0
  #define           rst_crc_reset                              1
 /* crc                            */
 #define    crc_ADDRESS                      890
 #define    crc_OFFSET                         0
 #define    crc_NBBIT                         16
 #define    crc_ALONE                          1
 #define    crc_SIGNED                         0
 /* gp_it1                         */
 #define    gp_it1_ADDRESS                   892
 #define    gp_it1_OFFSET                      0
 #define    gp_it1_NBBIT                       8
 #define    gp_it1_ALONE                       1
 #define    gp_it1_SIGNED                      0
 /* dcom_read                      */
 #define    dcom_read_ADDRESS                896
 #define    dcom_read_OFFSET                   0
 #define    dcom_read_NBBIT                   32
 #define    dcom_read_ALONE                    1
 #define    dcom_read_SIGNED                   0
 /* gp_reg0                        */
 #define    gp_reg0_ADDRESS                  900
 #define    gp_reg0_OFFSET                     0
 #define    gp_reg0_NBBIT                     32
 #define    gp_reg0_ALONE                      1
 #define    gp_reg0_SIGNED                     0
 /* gp_reg1                        */
 #define    gp_reg1_ADDRESS                  904
 #define    gp_reg1_OFFSET                     0
 #define    gp_reg1_NBBIT                     32
 #define    gp_reg1_ALONE                      1
 #define    gp_reg1_SIGNED                     0
 /* gp_reg2                        */
 #define    gp_reg2_ADDRESS                  908
 #define    gp_reg2_OFFSET                     0
 #define    gp_reg2_NBBIT                     32
 #define    gp_reg2_ALONE                      1
 #define    gp_reg2_SIGNED                     0
 /* demod_lock_t                   */
 #define    demod_lock_t_ADDRESS             912
 #define    demod_lock_t_OFFSET                0
 #define    demod_lock_t_NBBIT                 1
 #define    demod_lock_t_ALONE                 1
 #define    demod_lock_t_SIGNED                0
  #define           demod_lock_t_unlocked                      0
  #define           demod_lock_t_locked                        1
 /* tps_lock                       */
 #define    tps_lock_ADDRESS                 916
 #define    tps_lock_OFFSET                    0
 #define    tps_lock_NBBIT                     1
 #define    tps_lock_ALONE                     1
 #define    tps_lock_SIGNED                    0
  #define           tps_lock_unlocked                          0
  #define           tps_lock_locked                            1
 /* freq_lock_t                    */
 #define    freq_lock_t_ADDRESS              920
 #define    freq_lock_t_OFFSET                 0
 #define    freq_lock_t_NBBIT                  1
 #define    freq_lock_t_ALONE                  1
 #define    freq_lock_t_SIGNED                 0
  #define           freq_lock_t_unlocked                       0
  #define           freq_lock_t_locked                         1
 /* timing_lock_t                  */
 #define    timing_lock_t_ADDRESS            924
 #define    timing_lock_t_OFFSET               0
 #define    timing_lock_t_NBBIT                1
 #define    timing_lock_t_ALONE                1
 #define    timing_lock_t_SIGNED               0
  #define           timing_lock_t_unlocked                     0
  #define           timing_lock_t_locked                       1
 /* fft_lock_t                     */
 #define    fft_lock_t_ADDRESS               928
 #define    fft_lock_t_OFFSET                  0
 #define    fft_lock_t_NBBIT                   1
 #define    fft_lock_t_ALONE                   1
 #define    fft_lock_t_SIGNED                  0
  #define           fft_lock_t_unlocked                        0
  #define           fft_lock_t_locked                          1
 /* channel_length                 */
 #define    channel_length_ADDRESS           932
 #define    channel_length_OFFSET              0
 #define    channel_length_NBBIT              13
 #define    channel_length_ALONE               1
 #define    channel_length_SIGNED              0
 /* check_signal                   */
 #define    check_signal_ADDRESS             936
 #define    check_signal_OFFSET                0
 #define    check_signal_NBBIT                 2
 #define    check_signal_ALONE                 1
 #define    check_signal_SIGNED                0
  #define           check_signal_searching                     0
  #define           check_signal_nothing                       1
  #define           check_signal_digital                       2
 /* correl_lock                    */
 #define    correl_lock_ADDRESS              940
 #define    correl_lock_OFFSET                 0
 #define    correl_lock_NBBIT                  1
 #define    correl_lock_ALONE                  1
 #define    correl_lock_SIGNED                 0
  #define           correl_lock_unlocked                       0
  #define           correl_lock_locked                         1
 /* timing_corr_t                  */
 #define    timing_corr_t_ADDRESS            944
 #define    timing_corr_t_OFFSET               0
 #define    timing_corr_t_NBBIT               20
 #define    timing_corr_t_ALONE                1
 #define    timing_corr_t_SIGNED               1
 /* freq_corr_t                    */
 #define    freq_corr_t_ADDRESS              948
 #define    freq_corr_t_OFFSET                 0
 #define    freq_corr_t_NBBIT                 26
 #define    freq_corr_t_ALONE                  1
 #define    freq_corr_t_SIGNED                 1
 /* max_path_p                     */
 #define    max_path_p_ADDRESS               952
 #define    max_path_p_OFFSET                  0
 #define    max_path_p_NBBIT                   8
 #define    max_path_p_ALONE                   1
 #define    max_path_p_SIGNED                  0
 /* max_path_i                     */
 #define    max_path_i_ADDRESS               956
 #define    max_path_i_OFFSET                  0
 #define    max_path_i_NBBIT                   8
 #define    max_path_i_ALONE                   1
 #define    max_path_i_SIGNED                  0
 /* first_path_p                   */
 #define    first_path_p_ADDRESS             960
 #define    first_path_p_OFFSET                0
 #define    first_path_p_NBBIT                 8
 #define    first_path_p_ALONE                 1
 #define    first_path_p_SIGNED                0
 /* first_path_i                   */
 #define    first_path_i_ADDRESS             964
 #define    first_path_i_OFFSET                0
 #define    first_path_i_NBBIT                 8
 #define    first_path_i_ALONE                 1
 #define    first_path_i_SIGNED                0
 /* last_path_p                    */
 #define    last_path_p_ADDRESS              968
 #define    last_path_p_OFFSET                 0
 #define    last_path_p_NBBIT                  8
 #define    last_path_p_ALONE                  1
 #define    last_path_p_SIGNED                 0
 /* last_path_i                    */
 #define    last_path_i_ADDRESS              972
 #define    last_path_i_OFFSET                 0
 #define    last_path_i_NBBIT                  8
 #define    last_path_i_ALONE                  1
 #define    last_path_i_SIGNED                 0
 /* max2_path_p                    */
 #define    max2_path_p_ADDRESS              976
 #define    max2_path_p_OFFSET                 0
 #define    max2_path_p_NBBIT                  8
 #define    max2_path_p_ALONE                  1
 #define    max2_path_p_SIGNED                 0
 /* max2_path_i                    */
 #define    max2_path_i_ADDRESS              980
 #define    max2_path_i_OFFSET                 0
 #define    max2_path_i_NBBIT                  8
 #define    max2_path_i_ALONE                  1
 #define    max2_path_i_SIGNED                 0
 /* max3_path_p                    */
 #define    max3_path_p_ADDRESS              984
 #define    max3_path_p_OFFSET                 0
 #define    max3_path_p_NBBIT                  8
 #define    max3_path_p_ALONE                  1
 #define    max3_path_p_SIGNED                 0
 /* max3_path_i                    */
 #define    max3_path_i_ADDRESS              988
 #define    max3_path_i_OFFSET                 0
 #define    max3_path_i_NBBIT                  8
 #define    max3_path_i_ALONE                  1
 #define    max3_path_i_SIGNED                 0
 /* max4_path_p                    */
 #define    max4_path_p_ADDRESS              992
 #define    max4_path_p_OFFSET                 0
 #define    max4_path_p_NBBIT                  8
 #define    max4_path_p_ALONE                  1
 #define    max4_path_p_SIGNED                 0
 /* max4_path_i                    */
 #define    max4_path_i_ADDRESS              996
 #define    max4_path_i_OFFSET                 0
 #define    max4_path_i_NBBIT                  8
 #define    max4_path_i_ALONE                  1
 #define    max4_path_i_SIGNED                 0
 /* auto_fft_mode                  */
 #define    auto_fft_mode_ADDRESS            1008
 #define    auto_fft_mode_OFFSET               0
 #define    auto_fft_mode_NBBIT                4
 #define    auto_fft_mode_ALONE                1
 #define    auto_fft_mode_SIGNED               0
  #define           auto_fft_mode_2k                          11
  #define           auto_fft_mode_4k                          12
  #define           auto_fft_mode_8k                          13
 /* auto_guard_int                 */
 #define    auto_guard_int_ADDRESS           1012
 #define    auto_guard_int_OFFSET              0
 #define    auto_guard_int_NBBIT               3
 #define    auto_guard_int_ALONE               1
 #define    auto_guard_int_SIGNED              0
  #define           auto_guard_int_1_32                        1
  #define           auto_guard_int_1_16                        2
  #define           auto_guard_int_1_8                         3
  #define           auto_guard_int_1_4                         4
 /* auto_constellation             */
 #define    auto_constellation_ADDRESS       1016
 #define    auto_constellation_OFFSET          0
 #define    auto_constellation_NBBIT           6
 #define    auto_constellation_ALONE           1
 #define    auto_constellation_SIGNED          0
  #define           auto_constellation_qpsk                    3
  #define           auto_constellation_qam16                   7
  #define           auto_constellation_qam64                   9
 /* auto_rate_hp                   */
 #define    auto_rate_hp_ADDRESS             1024
 #define    auto_rate_hp_OFFSET                0
 #define    auto_rate_hp_NBBIT                 4
 #define    auto_rate_hp_ALONE                 1
 #define    auto_rate_hp_SIGNED                0
  #define           auto_rate_hp_1_2                           1
  #define           auto_rate_hp_2_3                           2
  #define           auto_rate_hp_3_4                           3
  #define           auto_rate_hp_5_6                           5
  #define           auto_rate_hp_7_8                           7
 /* auto_rate_lp                   */
 #define    auto_rate_lp_ADDRESS             1028
 #define    auto_rate_lp_OFFSET                0
 #define    auto_rate_lp_NBBIT                 4
 #define    auto_rate_lp_ALONE                 1
 #define    auto_rate_lp_SIGNED                0
  #define           auto_rate_lp_1_2                           1
  #define           auto_rate_lp_2_3                           2
  #define           auto_rate_lp_3_4                           3
  #define           auto_rate_lp_5_6                           5
  #define           auto_rate_lp_7_8                           7
 /* auto_hierarchy                 */
 #define    auto_hierarchy_ADDRESS           1032
 #define    auto_hierarchy_OFFSET              0
 #define    auto_hierarchy_NBBIT               3
 #define    auto_hierarchy_ALONE               1
 #define    auto_hierarchy_SIGNED              0
  #define           auto_hierarchy_none                        1
  #define           auto_hierarchy_alfa1                       2
  #define           auto_hierarchy_alfa2                       3
  #define           auto_hierarchy_alfa4                       5
 /* cell_id                        */
 #define    cell_id_ADDRESS                  1036
 #define    cell_id_OFFSET                     0
 #define    cell_id_NBBIT                     16
 #define    cell_id_ALONE                      1
 #define    cell_id_SIGNED                     0
 /* tps_reserved1                  */
 #define    tps_reserved1_ADDRESS            1040
 #define    tps_reserved1_OFFSET               0
 #define    tps_reserved1_NBBIT                4
 #define    tps_reserved1_ALONE                1
 #define    tps_reserved1_SIGNED               0
 /* tps_reserved2                  */
 #define    tps_reserved2_ADDRESS            1041
 #define    tps_reserved2_OFFSET               0
 #define    tps_reserved2_NBBIT                4
 #define    tps_reserved2_ALONE                1
 #define    tps_reserved2_SIGNED               0
 /* tps_reserved3                  */
 #define    tps_reserved3_ADDRESS            1042
 #define    tps_reserved3_OFFSET               0
 #define    tps_reserved3_NBBIT                4
 #define    tps_reserved3_ALONE                1
 #define    tps_reserved3_SIGNED               0
 /* tps_reserved4                  */
 #define    tps_reserved4_ADDRESS            1043
 #define    tps_reserved4_OFFSET               0
 #define    tps_reserved4_NBBIT                4
 #define    tps_reserved4_ALONE                1
 #define    tps_reserved4_SIGNED               0
 /* lp_time_slicing                */
 #define    lp_time_slicing_ADDRESS          1044
 #define    lp_time_slicing_OFFSET             0
 #define    lp_time_slicing_NBBIT              1
 #define    lp_time_slicing_ALONE              1
 #define    lp_time_slicing_SIGNED             0
  #define           lp_time_slicing_off                        0
  #define           lp_time_slicing_on                         1
 /* lp_mpe_fec                     */
 #define    lp_mpe_fec_ADDRESS               1045
 #define    lp_mpe_fec_OFFSET                  0
 #define    lp_mpe_fec_NBBIT                   1
 #define    lp_mpe_fec_ALONE                   1
 #define    lp_mpe_fec_SIGNED                  0
  #define           lp_mpe_fec_off                             0
  #define           lp_mpe_fec_on                              1
 /* hp_time_slicing                */
 #define    hp_time_slicing_ADDRESS          1046
 #define    hp_time_slicing_OFFSET             0
 #define    hp_time_slicing_NBBIT              1
 #define    hp_time_slicing_ALONE              1
 #define    hp_time_slicing_SIGNED             0
  #define           hp_time_slicing_off                        0
  #define           hp_time_slicing_on                         1
 /* hp_mpe_fec                     */
 #define    hp_mpe_fec_ADDRESS               1047
 #define    hp_mpe_fec_OFFSET                  0
 #define    hp_mpe_fec_NBBIT                   1
 #define    hp_mpe_fec_ALONE                   1
 #define    hp_mpe_fec_SIGNED                  0
  #define           hp_mpe_fec_off                             0
  #define           hp_mpe_fec_on                              1
 /* tps_length                     */
 #define    tps_length_ADDRESS               1048
 #define    tps_length_OFFSET                  0
 #define    tps_length_NBBIT                   6
 #define    tps_length_ALONE                   1
 #define    tps_length_SIGNED                  0
 /* dvbh_interleaver               */
 #define    dvbh_interleaver_ADDRESS         1052
 #define    dvbh_interleaver_OFFSET            0
 #define    dvbh_interleaver_NBBIT             1
 #define    dvbh_interleaver_ALONE             1
 #define    dvbh_interleaver_SIGNED            0
  #define           dvbh_interleaver_native                    0
  #define           dvbh_interleaver_in_depth                  1
 /* stream                         */
 #define    stream_ADDRESS                   1056
 #define    stream_OFFSET                      0
 #define    stream_NBBIT                       1
 #define    stream_ALONE                       1
 #define    stream_SIGNED                      0
  #define           stream_hp                                  0
  #define           stream_lp                                  1
 /* cber_rst                       */
 #define    cber_rst_ADDRESS                 1060
 #define    cber_rst_OFFSET                    0
 #define    cber_rst_NBBIT                     1
 #define    cber_rst_ALONE                     1
 #define    cber_rst_SIGNED                    0
  #define           cber_rst_run                               0
  #define           cber_rst_reset                             1
 /* cber_bit                       */
 #define    cber_bit_ADDRESS                 1064
 #define    cber_bit_OFFSET                    0
 #define    cber_bit_NBBIT                    24
 #define    cber_bit_ALONE                     1
 #define    cber_bit_SIGNED                    0
 /* cber_err                       */
 #define    cber_err_ADDRESS                 1072
 #define    cber_err_OFFSET                    0
 #define    cber_err_NBBIT                    24
 #define    cber_err_ALONE                     1
 #define    cber_err_SIGNED                    0
 /* cber_avail                     */
 #define    cber_avail_ADDRESS               1076
 #define    cber_avail_OFFSET                  0
 #define    cber_avail_NBBIT                   1
 #define    cber_avail_ALONE                   1
 #define    cber_avail_SIGNED                  0
  #define           cber_avail_unavailable                     0
  #define           cber_avail_available                       1
 /* ps_lock                        */
 #define    ps_lock_ADDRESS                  1088
 #define    ps_lock_OFFSET                     0
 #define    ps_lock_NBBIT                      1
 #define    ps_lock_ALONE                      1
 #define    ps_lock_SIGNED                     0
  #define           ps_lock_unlocked                           0
  #define           ps_lock_locked                             1
 /* ps_ambig_out                   */
 #define    ps_ambig_out_ADDRESS             1092
 #define    ps_ambig_out_OFFSET                0
 #define    ps_ambig_out_NBBIT                 1
 #define    ps_ambig_out_ALONE                 1
 #define    ps_ambig_out_SIGNED                0
 /* ps_stay_locked                 */
 #define    ps_stay_locked_ADDRESS           1096
 #define    ps_stay_locked_OFFSET              0
 #define    ps_stay_locked_NBBIT               1
 #define    ps_stay_locked_ALONE               1
 #define    ps_stay_locked_SIGNED              0
  #define           ps_stay_locked_unstay                      0
  #define           ps_stay_locked_stay                        1
 /* ps_sync_mode                   */
 #define    ps_sync_mode_ADDRESS             1100
 #define    ps_sync_mode_OFFSET                0
 #define    ps_sync_mode_NBBIT                 3
 #define    ps_sync_mode_ALONE                 1
 #define    ps_sync_mode_SIGNED                0
  #define           ps_sync_mode_auto                          0
  #define           ps_sync_mode_sframe                        1
  #define           ps_sync_mode_symbol                        2
 /* ps_sync_thr                    */
 #define    ps_sync_thr_ADDRESS              1101
 #define    ps_sync_thr_OFFSET                 0
 #define    ps_sync_thr_NBBIT                  4
 #define    ps_sync_thr_ALONE                  1
 #define    ps_sync_thr_SIGNED                 0
 /* ps_superv_thr                  */
 #define    ps_superv_thr_ADDRESS            1102
 #define    ps_superv_thr_OFFSET               0
 #define    ps_superv_thr_NBBIT                8
 #define    ps_superv_thr_ALONE                1
 #define    ps_superv_thr_SIGNED               0
 /* ps_ambig_thr                   */
 #define    ps_ambig_thr_ADDRESS             1103
 #define    ps_ambig_thr_OFFSET                0
 #define    ps_ambig_thr_NBBIT                 8
 #define    ps_ambig_thr_ALONE                 1
 #define    ps_ambig_thr_SIGNED                0
 /* ps_ambig_mode                  */
 #define    ps_ambig_mode_ADDRESS            1104
 #define    ps_ambig_mode_OFFSET               0
 #define    ps_ambig_mode_NBBIT                1
 #define    ps_ambig_mode_ALONE                0
 #define    ps_ambig_mode_SIGNED               0
  #define           ps_ambig_mode_manual                       0
  #define           ps_ambig_mode_auto                         1
 /* ps_ambig_reg                   */
 #define    ps_ambig_reg_ADDRESS             1104
 #define    ps_ambig_reg_OFFSET                1
 #define    ps_ambig_reg_NBBIT                 1
 #define    ps_ambig_reg_ALONE                 0
 #define    ps_ambig_reg_SIGNED                0
 /* rs_bypass                      */
 #define    rs_bypass_ADDRESS                1121
 #define    rs_bypass_OFFSET                   0
 #define    rs_bypass_NBBIT                    1
 #define    rs_bypass_ALONE                    1
 #define    rs_bypass_SIGNED                   0
  #define           rs_bypass_not_bypassed                     0
  #define           rs_bypass_bypassed                         1
 /* uncor_rst                      */
 #define    uncor_rst_ADDRESS                1124
 #define    uncor_rst_OFFSET                   0
 #define    uncor_rst_NBBIT                    1
 #define    uncor_rst_ALONE                    1
 #define    uncor_rst_SIGNED                   0
  #define           uncor_rst_reset                            1
  #define           uncor_rst_run                              0
 /* uncor_cnt                      */
 #define    uncor_cnt_ADDRESS                1128
 #define    uncor_cnt_OFFSET                   0
 #define    uncor_cnt_NBBIT                    8
 #define    uncor_cnt_ALONE                    1
 #define    uncor_cnt_SIGNED                   0
 /* ber_rst                        */
 #define    ber_rst_ADDRESS                  1132
 #define    ber_rst_OFFSET                     0
 #define    ber_rst_NBBIT                      1
 #define    ber_rst_ALONE                      1
 #define    ber_rst_SIGNED                     0
  #define           ber_rst_reset                              1
  #define           ber_rst_run                                0
 /* ber_pkt                        */
 #define    ber_pkt_ADDRESS                  1136
 #define    ber_pkt_OFFSET                     0
 #define    ber_pkt_NBBIT                     16
 #define    ber_pkt_ALONE                      1
 #define    ber_pkt_SIGNED                     0
 /* ber_bit                        */
 #define    ber_bit_ADDRESS                  1144
 #define    ber_bit_OFFSET                     0
 #define    ber_bit_NBBIT                     24
 #define    ber_bit_ALONE                      1
 #define    ber_bit_SIGNED                     0
 /* ber_avail                      */
 #define    ber_avail_ADDRESS                1148
 #define    ber_avail_OFFSET                   0
 #define    ber_avail_NBBIT                    1
 #define    ber_avail_ALONE                    1
 #define    ber_avail_SIGNED                   0
  #define           ber_avail_unavailable                      0
  #define           ber_avail_available                        1
 /* per_rst                        */
 #define    per_rst_ADDRESS                  1152
 #define    per_rst_OFFSET                     0
 #define    per_rst_NBBIT                      1
 #define    per_rst_ALONE                      1
 #define    per_rst_SIGNED                     0
  #define           per_rst_run                                0
  #define           per_rst_reset                              1
 /* per_pkt                        */
 #define    per_pkt_ADDRESS                  1156
 #define    per_pkt_OFFSET                     0
 #define    per_pkt_NBBIT                     16
 #define    per_pkt_ALONE                      1
 #define    per_pkt_SIGNED                     0
 /* per                            */
 #define    per_ADDRESS                      1164
 #define    per_OFFSET                         0
 #define    per_NBBIT                         16
 #define    per_ALONE                          1
 #define    per_SIGNED                         0
 /* per_avail                      */
 #define    per_avail_ADDRESS                1168
 #define    per_avail_OFFSET                   0
 #define    per_avail_NBBIT                    1
 #define    per_avail_ALONE                    1
 #define    per_avail_SIGNED                   0
  #define           per_avail_unavailable                      0
  #define           per_avail_available                        1
 /* ber2_rst                       */
 #define    ber2_rst_ADDRESS                 1172
 #define    ber2_rst_OFFSET                    0
 #define    ber2_rst_NBBIT                     1
 #define    ber2_rst_ALONE                     1
 #define    ber2_rst_SIGNED                    0
  #define           ber2_rst_run                               0
  #define           ber2_rst_reset                             1
 /* ber2_pkt                       */
 #define    ber2_pkt_ADDRESS                 1176
 #define    ber2_pkt_OFFSET                    0
 #define    ber2_pkt_NBBIT                    16
 #define    ber2_pkt_ALONE                     1
 #define    ber2_pkt_SIGNED                    0
 /* ber2_bit                       */
 #define    ber2_bit_ADDRESS                 1184
 #define    ber2_bit_OFFSET                    0
 #define    ber2_bit_NBBIT                    24
 #define    ber2_bit_ALONE                     1
 #define    ber2_bit_SIGNED                    0
 /* ber2_avail                     */
 #define    ber2_avail_ADDRESS               1188
 #define    ber2_avail_OFFSET                  0
 #define    ber2_avail_NBBIT                   1
 #define    ber2_avail_ALONE                   1
 #define    ber2_avail_SIGNED                  0
  #define           ber2_avail_unavailable                     0
  #define           ber2_avail_available                       1
 /* per2_rst                       */
 #define    per2_rst_ADDRESS                 1192
 #define    per2_rst_OFFSET                    0
 #define    per2_rst_NBBIT                     1
 #define    per2_rst_ALONE                     1
 #define    per2_rst_SIGNED                    0
  #define           per2_rst_run                               0
  #define           per2_rst_reset                             1
 /* per2_pkt                       */
 #define    per2_pkt_ADDRESS                 1196
 #define    per2_pkt_OFFSET                    0
 #define    per2_pkt_NBBIT                    16
 #define    per2_pkt_ALONE                     1
 #define    per2_pkt_SIGNED                    0
 /* per2                           */
 #define    per2_ADDRESS                     1204
 #define    per2_OFFSET                        0
 #define    per2_NBBIT                        16
 #define    per2_ALONE                         1
 #define    per2_SIGNED                        0
 /* per2_avail                     */
 #define    per2_avail_ADDRESS               1208
 #define    per2_avail_OFFSET                  0
 #define    per2_avail_NBBIT                   1
 #define    per2_avail_ALONE                   1
 #define    per2_avail_SIGNED                  0
  #define           per2_avail_unavailable                     0
  #define           per2_avail_available                       1
 /* symb_deint_mode                */
 #define    symb_deint_mode_ADDRESS          1216
 #define    symb_deint_mode_OFFSET             0
 #define    symb_deint_mode_NBBIT              1
 #define    symb_deint_mode_ALONE              1
 #define    symb_deint_mode_SIGNED             0
  #define           symb_deint_mode_native                     0
  #define           symb_deint_mode_in_depth                   1
 /* out_deint_bypass               */
 #define    out_deint_bypass_ADDRESS         1222
 #define    out_deint_bypass_OFFSET            0
 #define    out_deint_bypass_NBBIT             1
 #define    out_deint_bypass_ALONE             1
 #define    out_deint_bypass_SIGNED            0
  #define           out_deint_bypass_not_bypassed              0
  #define           out_deint_bypass_bypassed                  1
 /* bit_deint_bypass               */
 #define    bit_deint_bypass_ADDRESS         1223
 #define    bit_deint_bypass_OFFSET            0
 #define    bit_deint_bypass_NBBIT             1
 #define    bit_deint_bypass_ALONE             1
 #define    bit_deint_bypass_SIGNED            0
  #define           bit_deint_bypass_not_bypassed              0
  #define           bit_deint_bypass_bypassed                  1
 /* symb_deint_bypass              */
 #define    symb_deint_bypass_ADDRESS        1224
 #define    symb_deint_bypass_OFFSET           0
 #define    symb_deint_bypass_NBBIT            1
 #define    symb_deint_bypass_ALONE            1
 #define    symb_deint_bypass_SIGNED           0
  #define           symb_deint_bypass_not_bypassed             0
  #define           symb_deint_bypass_bypassed                 1
 /* desc_enable                    */
 #define    desc_enable_ADDRESS              1232
 #define    desc_enable_OFFSET                 0
 #define    desc_enable_NBBIT                  1
 #define    desc_enable_ALONE                  1
 #define    desc_enable_SIGNED                 0
  #define           desc_enable_disabled                       0
  #define           desc_enable_enabled                        1
 /* desc_stay_locked               */
 #define    desc_stay_locked_ADDRESS         1236
 #define    desc_stay_locked_OFFSET            0
 #define    desc_stay_locked_NBBIT             1
 #define    desc_stay_locked_ALONE             1
 #define    desc_stay_locked_SIGNED            0
  #define           desc_stay_locked_unstay                    0
  #define           desc_stay_locked_stay                      1
 /* desc_sync_thr                  */
 #define    desc_sync_thr_ADDRESS            1241
 #define    desc_sync_thr_OFFSET               0
 #define    desc_sync_thr_NBBIT                4
 #define    desc_sync_thr_ALONE                1
 #define    desc_sync_thr_SIGNED               0
 /* desc_superv_thr                */
 #define    desc_superv_thr_ADDRESS          1242
 #define    desc_superv_thr_OFFSET             0
 #define    desc_superv_thr_NBBIT              6
 #define    desc_superv_thr_ALONE              1
 #define    desc_superv_thr_SIGNED             0
 /* fec_lock                       */
 #define    fec_lock_ADDRESS                 1248
 #define    fec_lock_OFFSET                    0
 #define    fec_lock_NBBIT                     1
 #define    fec_lock_ALONE                     1
 #define    fec_lock_SIGNED                    0
  #define           fec_lock_unlocked                          0
  #define           fec_lock_locked                            1
 /* ts_data_mode                   */
 #define    ts_data_mode_ADDRESS             1252
 #define    ts_data_mode_OFFSET                0
 #define    ts_data_mode_NBBIT                 1
 #define    ts_data_mode_ALONE                 0
 #define    ts_data_mode_SIGNED                0
  #define           ts_data_mode_serial                        0
  #define           ts_data_mode_parallel                      1
 /* ts_data_dir                    */
 #define    ts_data_dir_ADDRESS              1252
 #define    ts_data_dir_OFFSET                 1
 #define    ts_data_dir_NBBIT                  1
 #define    ts_data_dir_ALONE                  0
 #define    ts_data_dir_SIGNED                 0
  #define           ts_data_dir_msb_first                      0
  #define           ts_data_dir_lsb_first                      1
 /* ts_data_parity                 */
 #define    ts_data_parity_ADDRESS           1252
 #define    ts_data_parity_OFFSET              2
 #define    ts_data_parity_NBBIT               1
 #define    ts_data_parity_ALONE               0
 #define    ts_data_parity_SIGNED              0
  #define           ts_data_parity_enabled                     0
  #define           ts_data_parity_disabled                    1
 /* ts_data_sync_overwr            */
 #define    ts_data_sync_overwr_ADDRESS      1252
 #define    ts_data_sync_overwr_OFFSET         3
 #define    ts_data_sync_overwr_NBBIT          1
 #define    ts_data_sync_overwr_ALONE          0
 #define    ts_data_sync_overwr_SIGNED         0
  #define           ts_data_sync_overwr_enabled                0
  #define           ts_data_sync_overwr_disabled               1
 /* ts_tei                         */
 #define    ts_tei_ADDRESS                   1252
 #define    ts_tei_OFFSET                      4
 #define    ts_tei_NBBIT                       1
 #define    ts_tei_ALONE                       0
 #define    ts_tei_SIGNED                      0
  #define           ts_tei_enabled                             0
  #define           ts_tei_disabled                            1
 /* ts_before_lock                 */
 #define    ts_before_lock_ADDRESS           1252
 #define    ts_before_lock_OFFSET              5
 #define    ts_before_lock_NBBIT               1
 #define    ts_before_lock_ALONE               0
 #define    ts_before_lock_SIGNED              0
  #define           ts_before_lock_active                      0
  #define           ts_before_lock_quiet                       1
 /* ts_clk_edge                    */
 #define    ts_clk_edge_ADDRESS              1253
 #define    ts_clk_edge_OFFSET                 0
 #define    ts_clk_edge_NBBIT                  1
 #define    ts_clk_edge_ALONE                  0
 #define    ts_clk_edge_SIGNED                 0
  #define           ts_clk_edge_rising                         0
  #define           ts_clk_edge_falling                        1
 /* ts_clk_mode                    */
 #define    ts_clk_mode_ADDRESS              1253
 #define    ts_clk_mode_OFFSET                 1
 #define    ts_clk_mode_NBBIT                  1
 #define    ts_clk_mode_ALONE                  0
 #define    ts_clk_mode_SIGNED                 0
  #define           ts_clk_mode_gapped                         0
  #define           ts_clk_mode_continuous                     1
 /* ts_clk_duty_cycle              */
 #define    ts_clk_duty_cycle_ADDRESS        1253
 #define    ts_clk_duty_cycle_OFFSET           2
 #define    ts_clk_duty_cycle_NBBIT            1
 #define    ts_clk_duty_cycle_ALONE            0
 #define    ts_clk_duty_cycle_SIGNED           0
 /* ts_sync_length                 */
 #define    ts_sync_length_ADDRESS           1254
 #define    ts_sync_length_OFFSET              0
 #define    ts_sync_length_NBBIT               1
 #define    ts_sync_length_ALONE               0
 #define    ts_sync_length_SIGNED              0
  #define           ts_sync_length_first_byte                  0
  #define           ts_sync_length_first_bit                   1
 /* ts_sync_pola                   */
 #define    ts_sync_pola_ADDRESS             1254
 #define    ts_sync_pola_OFFSET                1
 #define    ts_sync_pola_NBBIT                 1
 #define    ts_sync_pola_ALONE                 0
 #define    ts_sync_pola_SIGNED                0
  #define           ts_sync_pola_active_high                   0
  #define           ts_sync_pola_active_low                    1
 /* ts_val_pola                    */
 #define    ts_val_pola_ADDRESS              1254
 #define    ts_val_pola_OFFSET                 2
 #define    ts_val_pola_NBBIT                  1
 #define    ts_val_pola_ALONE                  0
 #define    ts_val_pola_SIGNED                 0
  #define           ts_val_pola_active_high                    0
  #define           ts_val_pola_active_low                     1
 /* ts_err_pola                    */
 #define    ts_err_pola_ADDRESS              1254
 #define    ts_err_pola_OFFSET                 3
 #define    ts_err_pola_NBBIT                  1
 #define    ts_err_pola_ALONE                  0
 #define    ts_err_pola_SIGNED                 0
  #define           ts_err_pola_active_high                    0
  #define           ts_err_pola_active_low                     1
 /* ts_mux                         */
 #define    ts_mux_ADDRESS                   1257
 #define    ts_mux_OFFSET                      0
 #define    ts_mux_NBBIT                       3
 #define    ts_mux_ALONE                       1
 #define    ts_mux_SIGNED                      0
  #define           ts_mux_ts                                  0
  #define           ts_mux_gpif                                1
  #define           ts_mux_tst                                 2
  #define           ts_mux_sdi_iq                              3
  #define           ts_mux_adc_i                               4
  #define           ts_mux_adc_q                               5
  #define           ts_mux_adc_iq                              6
  #define           ts_mux_clocks                              7
 /* sel_gpio_ts_err                */
 #define    sel_gpio_ts_err_ADDRESS          1259
 #define    sel_gpio_ts_err_OFFSET             0
 #define    sel_gpio_ts_err_NBBIT              1
 #define    sel_gpio_ts_err_ALONE              0
 #define    sel_gpio_ts_err_SIGNED             0
  #define           sel_gpio_ts_err_ts_err                     0
  #define           sel_gpio_ts_err_gpio_2                     1
 /* sel_gpio_ts_data1              */
 #define    sel_gpio_ts_data1_ADDRESS        1259
 #define    sel_gpio_ts_data1_OFFSET           1
 #define    sel_gpio_ts_data1_NBBIT            1
 #define    sel_gpio_ts_data1_ALONE            0
 #define    sel_gpio_ts_data1_SIGNED           0
  #define           sel_gpio_ts_data1_ts_data                  0
  #define           sel_gpio_ts_data1_gpio_1                   1
 /* sel_gpio_ts_data2              */
 #define    sel_gpio_ts_data2_ADDRESS        1259
 #define    sel_gpio_ts_data2_OFFSET           2
 #define    sel_gpio_ts_data2_NBBIT            1
 #define    sel_gpio_ts_data2_ALONE            0
 #define    sel_gpio_ts_data2_SIGNED           0
  #define           sel_gpio_ts_data2_ts_data                  0
  #define           sel_gpio_ts_data2_gpio_3                   1
 /* sel_gpio_ts_data3              */
 #define    sel_gpio_ts_data3_ADDRESS        1259
 #define    sel_gpio_ts_data3_OFFSET           3
 #define    sel_gpio_ts_data3_NBBIT            1
 #define    sel_gpio_ts_data3_ALONE            0
 #define    sel_gpio_ts_data3_SIGNED           0
  #define           sel_gpio_ts_data3_ts_data                  0
  #define           sel_gpio_ts_data3_gpio_4                   1
 /* sel_gpio_ts_data4              */
 #define    sel_gpio_ts_data4_ADDRESS        1259
 #define    sel_gpio_ts_data4_OFFSET           4
 #define    sel_gpio_ts_data4_NBBIT            1
 #define    sel_gpio_ts_data4_ALONE            0
 #define    sel_gpio_ts_data4_SIGNED           0
  #define           sel_gpio_ts_data4_ts_data                  0
  #define           sel_gpio_ts_data4_gpio_5                   1
 /* ts_data0_tri                   */
 #define    ts_data0_tri_ADDRESS             1263
 #define    ts_data0_tri_OFFSET                0
 #define    ts_data0_tri_NBBIT                 1
 #define    ts_data0_tri_ALONE                 0
 #define    ts_data0_tri_SIGNED                0
  #define           ts_data0_tri_normal                        0
  #define           ts_data0_tri_tristate                      1
 /* ts_data1_tri                   */
 #define    ts_data1_tri_ADDRESS             1263
 #define    ts_data1_tri_OFFSET                1
 #define    ts_data1_tri_NBBIT                 1
 #define    ts_data1_tri_ALONE                 0
 #define    ts_data1_tri_SIGNED                0
  #define           ts_data1_tri_normal                        0
  #define           ts_data1_tri_tristate                      1
 /* ts_data2_tri                   */
 #define    ts_data2_tri_ADDRESS             1263
 #define    ts_data2_tri_OFFSET                2
 #define    ts_data2_tri_NBBIT                 1
 #define    ts_data2_tri_ALONE                 0
 #define    ts_data2_tri_SIGNED                0
  #define           ts_data2_tri_normal                        0
  #define           ts_data2_tri_tristate                      1
 /* ts_data3_tri                   */
 #define    ts_data3_tri_ADDRESS             1263
 #define    ts_data3_tri_OFFSET                3
 #define    ts_data3_tri_NBBIT                 1
 #define    ts_data3_tri_ALONE                 0
 #define    ts_data3_tri_SIGNED                0
  #define           ts_data3_tri_normal                        0
  #define           ts_data3_tri_tristate                      1
 /* ts_data4_tri                   */
 #define    ts_data4_tri_ADDRESS             1263
 #define    ts_data4_tri_OFFSET                4
 #define    ts_data4_tri_NBBIT                 1
 #define    ts_data4_tri_ALONE                 0
 #define    ts_data4_tri_SIGNED                0
  #define           ts_data4_tri_normal                        0
  #define           ts_data4_tri_tristate                      1
 /* ts_data5_tri                   */
 #define    ts_data5_tri_ADDRESS             1263
 #define    ts_data5_tri_OFFSET                5
 #define    ts_data5_tri_NBBIT                 1
 #define    ts_data5_tri_ALONE                 0
 #define    ts_data5_tri_SIGNED                0
  #define           ts_data5_tri_normal                        0
  #define           ts_data5_tri_tristate                      1
 /* ts_data6_tri                   */
 #define    ts_data6_tri_ADDRESS             1263
 #define    ts_data6_tri_OFFSET                6
 #define    ts_data6_tri_NBBIT                 1
 #define    ts_data6_tri_ALONE                 0
 #define    ts_data6_tri_SIGNED                0
  #define           ts_data6_tri_normal                        0
  #define           ts_data6_tri_tristate                      1
 /* ts_data7_tri                   */
 #define    ts_data7_tri_ADDRESS             1263
 #define    ts_data7_tri_OFFSET                7
 #define    ts_data7_tri_NBBIT                 1
 #define    ts_data7_tri_ALONE                 0
 #define    ts_data7_tri_SIGNED                0
  #define           ts_data7_tri_normal                        0
  #define           ts_data7_tri_tristate                      1
 /* ts_val_tri                     */
 #define    ts_val_tri_ADDRESS               1264
 #define    ts_val_tri_OFFSET                  0
 #define    ts_val_tri_NBBIT                   1
 #define    ts_val_tri_ALONE                   0
 #define    ts_val_tri_SIGNED                  0
  #define           ts_val_tri_normal                          0
  #define           ts_val_tri_tristate                        1
 /* ts_sync_tri                    */
 #define    ts_sync_tri_ADDRESS              1264
 #define    ts_sync_tri_OFFSET                 1
 #define    ts_sync_tri_NBBIT                  1
 #define    ts_sync_tri_ALONE                  0
 #define    ts_sync_tri_SIGNED                 0
  #define           ts_sync_tri_normal                         0
  #define           ts_sync_tri_tristate                       1
 /* ts_err_tri                     */
 #define    ts_err_tri_ADDRESS               1264
 #define    ts_err_tri_OFFSET                  2
 #define    ts_err_tri_NBBIT                   1
 #define    ts_err_tri_ALONE                   0
 #define    ts_err_tri_SIGNED                  0
  #define           ts_err_tri_normal                          0
  #define           ts_err_tri_tristate                        1
 /* ts_clk_tri                     */
 #define    ts_clk_tri_ADDRESS               1264
 #define    ts_clk_tri_OFFSET                  3
 #define    ts_clk_tri_NBBIT                   1
 #define    ts_clk_tri_ALONE                   0
 #define    ts_clk_tri_SIGNED                  0
  #define           ts_clk_tri_normal                          0
  #define           ts_clk_tri_tristate                        1
 /* ts_data0_slr                   */
 #define    ts_data0_slr_ADDRESS             1268
 #define    ts_data0_slr_OFFSET                0
 #define    ts_data0_slr_NBBIT                 2
 #define    ts_data0_slr_ALONE                 0
 #define    ts_data0_slr_SIGNED                0
  #define           ts_data0_slr_fastest edges                 0
  #define           ts_data0_slr_slowest edges                 1
  #define           ts_data0_slr_moderate edges                2
  #define           ts_data0_slr_fast edges                    3
 /* ts_data1_slr                   */
 #define    ts_data1_slr_ADDRESS             1268
 #define    ts_data1_slr_OFFSET                2
 #define    ts_data1_slr_NBBIT                 2
 #define    ts_data1_slr_ALONE                 0
 #define    ts_data1_slr_SIGNED                0
  #define           ts_data1_slr_fastest edges                 0
  #define           ts_data1_slr_slowest edges                 1
  #define           ts_data1_slr_moderate edges                2
  #define           ts_data1_slr_fast edges                    3
 /* ts_data2_slr                   */
 #define    ts_data2_slr_ADDRESS             1268
 #define    ts_data2_slr_OFFSET                4
 #define    ts_data2_slr_NBBIT                 2
 #define    ts_data2_slr_ALONE                 0
 #define    ts_data2_slr_SIGNED                0
  #define           ts_data2_slr_fastest edges                 0
  #define           ts_data2_slr_slowest edges                 1
  #define           ts_data2_slr_moderate edges                2
  #define           ts_data2_slr_fast edges                    3
 /* ts_data3_slr                   */
 #define    ts_data3_slr_ADDRESS             1268
 #define    ts_data3_slr_OFFSET                6
 #define    ts_data3_slr_NBBIT                 2
 #define    ts_data3_slr_ALONE                 0
 #define    ts_data3_slr_SIGNED                0
  #define           ts_data3_slr_fastest edges                 0
  #define           ts_data3_slr_slowest edges                 1
  #define           ts_data3_slr_moderate edges                2
  #define           ts_data3_slr_fast edges                    3
 /* ts_data4_slr                   */
 #define    ts_data4_slr_ADDRESS             1269
 #define    ts_data4_slr_OFFSET                0
 #define    ts_data4_slr_NBBIT                 2
 #define    ts_data4_slr_ALONE                 0
 #define    ts_data4_slr_SIGNED                0
  #define           ts_data4_slr_fastest edges                 0
  #define           ts_data4_slr_slowest edges                 1
  #define           ts_data4_slr_moderate edges                2
  #define           ts_data4_slr_fast edges                    3
 /* ts_data5_slr                   */
 #define    ts_data5_slr_ADDRESS             1269
 #define    ts_data5_slr_OFFSET                2
 #define    ts_data5_slr_NBBIT                 2
 #define    ts_data5_slr_ALONE                 0
 #define    ts_data5_slr_SIGNED                0
  #define           ts_data5_slr_fastest edges                 0
  #define           ts_data5_slr_slowest edges                 1
  #define           ts_data5_slr_moderate edges                2
  #define           ts_data5_slr_fast edges                    3
 /* ts_data6_slr                   */
 #define    ts_data6_slr_ADDRESS             1269
 #define    ts_data6_slr_OFFSET                4
 #define    ts_data6_slr_NBBIT                 2
 #define    ts_data6_slr_ALONE                 0
 #define    ts_data6_slr_SIGNED                0
  #define           ts_data6_slr_fastest edges                 0
  #define           ts_data6_slr_slowest edges                 1
  #define           ts_data6_slr_moderate edges                2
  #define           ts_data6_slr_fast edges                    3
 /* ts_data7_slr                   */
 #define    ts_data7_slr_ADDRESS             1269
 #define    ts_data7_slr_OFFSET                6
 #define    ts_data7_slr_NBBIT                 2
 #define    ts_data7_slr_ALONE                 0
 #define    ts_data7_slr_SIGNED                0
  #define           ts_data7_slr_fastest edges                 0
  #define           ts_data7_slr_slowest edges                 1
  #define           ts_data7_slr_moderate edges                2
  #define           ts_data7_slr_fast edges                    3
 /* ts_val_slr                     */
 #define    ts_val_slr_ADDRESS               1270
 #define    ts_val_slr_OFFSET                  0
 #define    ts_val_slr_NBBIT                   2
 #define    ts_val_slr_ALONE                   0
 #define    ts_val_slr_SIGNED                  0
  #define           ts_val_slr_fastest edges                   0
  #define           ts_val_slr_slowest edges                   1
  #define           ts_val_slr_moderate edges                  2
  #define           ts_val_slr_fast edges                      3
 /* ts_sync_slr                    */
 #define    ts_sync_slr_ADDRESS              1270
 #define    ts_sync_slr_OFFSET                 2
 #define    ts_sync_slr_NBBIT                  2
 #define    ts_sync_slr_ALONE                  0
 #define    ts_sync_slr_SIGNED                 0
  #define           ts_sync_slr_fastest edges                  0
  #define           ts_sync_slr_slowest edges                  1
  #define           ts_sync_slr_moderate edges                 2
  #define           ts_sync_slr_fast edges                     3
 /* ts_err_slr                     */
 #define    ts_err_slr_ADDRESS               1270
 #define    ts_err_slr_OFFSET                  4
 #define    ts_err_slr_NBBIT                   2
 #define    ts_err_slr_ALONE                   0
 #define    ts_err_slr_SIGNED                  0
  #define           ts_err_slr_fastest edges                   0
  #define           ts_err_slr_slowest edges                   1
  #define           ts_err_slr_moderate edges                  2
  #define           ts_err_slr_fast edges                      3
 /* ts_clk_slr                     */
 #define    ts_clk_slr_ADDRESS               1270
 #define    ts_clk_slr_OFFSET                  6
 #define    ts_clk_slr_NBBIT                   2
 #define    ts_clk_slr_ALONE                   0
 #define    ts_clk_slr_SIGNED                  0
  #define           ts_clk_slr_fastest edges                   0
  #define           ts_clk_slr_slowest edges                   1
  #define           ts_clk_slr_moderate edges                  2
  #define           ts_clk_slr_fast edges                      3
 /* gpif_in_fifo_overflow          */
 #define    gpif_in_fifo_overflow_ADDRESS    1280
 #define    gpif_in_fifo_overflow_OFFSET       0
 #define    gpif_in_fifo_overflow_NBBIT        1
 #define    gpif_in_fifo_overflow_ALONE        0
 #define    gpif_in_fifo_overflow_SIGNED       0
  #define           gpif_in_fifo_overflow_none                 0
  #define           gpif_in_fifo_overflow_overflow             1
 /* gpif_ram_overflow              */
 #define    gpif_ram_overflow_ADDRESS        1280
 #define    gpif_ram_overflow_OFFSET           1
 #define    gpif_ram_overflow_NBBIT            1
 #define    gpif_ram_overflow_ALONE            0
 #define    gpif_ram_overflow_SIGNED           0
  #define           gpif_ram_overflow_none                     0
  #define           gpif_ram_overflow_overflow                 1
 /* gpif_standby                   */
 #define    gpif_standby_ADDRESS             1280
 #define    gpif_standby_OFFSET                2
 #define    gpif_standby_NBBIT                 1
 #define    gpif_standby_ALONE                 0
 #define    gpif_standby_SIGNED                0
  #define           gpif_standby_run                           0
  #define           gpif_standby_standby                       1
 /* gpif_alarm_reset               */
 #define    gpif_alarm_reset_ADDRESS         1284
 #define    gpif_alarm_reset_OFFSET            0
 #define    gpif_alarm_reset_NBBIT             1
 #define    gpif_alarm_reset_ALONE             1
 #define    gpif_alarm_reset_SIGNED            0
  #define           gpif_alarm_reset_run                       0
  #define           gpif_alarm_reset_reset                     1
 /* pid_filter_en                  */
 #define    pid_filter_en_ADDRESS            1296
 #define    pid_filter_en_OFFSET               0
 #define    pid_filter_en_NBBIT                1
 #define    pid_filter_en_ALONE                0
 #define    pid_filter_en_SIGNED               0
  #define           pid_filter_en_bypass                       0
  #define           pid_filter_en_on                           1
 /* pid_p                          */
 #define    pid_p_ADDRESS                    1296
 #define    pid_p_OFFSET                       1
 #define    pid_p_NBBIT                        1
 #define    pid_p_ALONE                        0
 #define    pid_p_SIGNED                       0
  #define           pid_p_negative                             0
  #define           pid_p_positive                             1
 /* pid_en_0                       */
 #define    pid_en_0_ADDRESS                 1300
 #define    pid_en_0_OFFSET                    0
 #define    pid_en_0_NBBIT                     1
 #define    pid_en_0_ALONE                     0
 #define    pid_en_0_SIGNED                    0
  #define           pid_en_0_off                               0
  #define           pid_en_0_enable                            1
 /* pid_en_1                       */
 #define    pid_en_1_ADDRESS                 1300
 #define    pid_en_1_OFFSET                    1
 #define    pid_en_1_NBBIT                     1
 #define    pid_en_1_ALONE                     0
 #define    pid_en_1_SIGNED                    0
  #define           pid_en_1_off                               0
  #define           pid_en_1_enable                            1
 /* pid_en_2                       */
 #define    pid_en_2_ADDRESS                 1300
 #define    pid_en_2_OFFSET                    2
 #define    pid_en_2_NBBIT                     1
 #define    pid_en_2_ALONE                     0
 #define    pid_en_2_SIGNED                    0
  #define           pid_en_2_off                               0
  #define           pid_en_2_enable                            1
 /* pid_en_3                       */
 #define    pid_en_3_ADDRESS                 1300
 #define    pid_en_3_OFFSET                    3
 #define    pid_en_3_NBBIT                     1
 #define    pid_en_3_ALONE                     0
 #define    pid_en_3_SIGNED                    0
  #define           pid_en_3_off                               0
  #define           pid_en_3_enable                            1
 /* pid_en_4                       */
 #define    pid_en_4_ADDRESS                 1300
 #define    pid_en_4_OFFSET                    4
 #define    pid_en_4_NBBIT                     1
 #define    pid_en_4_ALONE                     0
 #define    pid_en_4_SIGNED                    0
  #define           pid_en_4_off                               0
  #define           pid_en_4_enable                            1
 /* pid_en_5                       */
 #define    pid_en_5_ADDRESS                 1300
 #define    pid_en_5_OFFSET                    5
 #define    pid_en_5_NBBIT                     1
 #define    pid_en_5_ALONE                     0
 #define    pid_en_5_SIGNED                    0
  #define           pid_en_5_off                               0
  #define           pid_en_5_enable                            1
 /* pid_en_6                       */
 #define    pid_en_6_ADDRESS                 1300
 #define    pid_en_6_OFFSET                    6
 #define    pid_en_6_NBBIT                     1
 #define    pid_en_6_ALONE                     0
 #define    pid_en_6_SIGNED                    0
  #define           pid_en_6_off                               0
  #define           pid_en_6_enable                            1
 /* pid_en_7                       */
 #define    pid_en_7_ADDRESS                 1300
 #define    pid_en_7_OFFSET                    7
 #define    pid_en_7_NBBIT                     1
 #define    pid_en_7_ALONE                     0
 #define    pid_en_7_SIGNED                    0
  #define           pid_en_7_off                               0
  #define           pid_en_7_enable                            1
 /* pid_en_8                       */
 #define    pid_en_8_ADDRESS                 1301
 #define    pid_en_8_OFFSET                    0
 #define    pid_en_8_NBBIT                     1
 #define    pid_en_8_ALONE                     0
 #define    pid_en_8_SIGNED                    0
  #define           pid_en_8_off                               0
  #define           pid_en_8_enable                            1
 /* pid_en_9                       */
 #define    pid_en_9_ADDRESS                 1301
 #define    pid_en_9_OFFSET                    1
 #define    pid_en_9_NBBIT                     1
 #define    pid_en_9_ALONE                     0
 #define    pid_en_9_SIGNED                    0
  #define           pid_en_9_off                               0
  #define           pid_en_9_enable                            1
 /* pid_en_10                      */
 #define    pid_en_10_ADDRESS                1301
 #define    pid_en_10_OFFSET                   2
 #define    pid_en_10_NBBIT                    1
 #define    pid_en_10_ALONE                    0
 #define    pid_en_10_SIGNED                   0
  #define           pid_en_10_off                              0
  #define           pid_en_10_enable                           1
 /* pid_en_11                      */
 #define    pid_en_11_ADDRESS                1301
 #define    pid_en_11_OFFSET                   3
 #define    pid_en_11_NBBIT                    1
 #define    pid_en_11_ALONE                    0
 #define    pid_en_11_SIGNED                   0
  #define           pid_en_11_off                              0
  #define           pid_en_11_enable                           1
 /* pid_en_12                      */
 #define    pid_en_12_ADDRESS                1301
 #define    pid_en_12_OFFSET                   4
 #define    pid_en_12_NBBIT                    1
 #define    pid_en_12_ALONE                    0
 #define    pid_en_12_SIGNED                   0
  #define           pid_en_12_off                              0
  #define           pid_en_12_enable                           1
 /* pid_en_13                      */
 #define    pid_en_13_ADDRESS                1301
 #define    pid_en_13_OFFSET                   5
 #define    pid_en_13_NBBIT                    1
 #define    pid_en_13_ALONE                    0
 #define    pid_en_13_SIGNED                   0
  #define           pid_en_13_off                              0
  #define           pid_en_13_enable                           1
 /* pid_en_14                      */
 #define    pid_en_14_ADDRESS                1301
 #define    pid_en_14_OFFSET                   6
 #define    pid_en_14_NBBIT                    1
 #define    pid_en_14_ALONE                    0
 #define    pid_en_14_SIGNED                   0
  #define           pid_en_14_off                              0
  #define           pid_en_14_enable                           1
 /* pid_en_15                      */
 #define    pid_en_15_ADDRESS                1301
 #define    pid_en_15_OFFSET                   7
 #define    pid_en_15_NBBIT                    1
 #define    pid_en_15_ALONE                    0
 #define    pid_en_15_SIGNED                   0
  #define           pid_en_15_off                              0
  #define           pid_en_15_enable                           1
 /* pid_en_16                      */
 #define    pid_en_16_ADDRESS                1302
 #define    pid_en_16_OFFSET                   0
 #define    pid_en_16_NBBIT                    1
 #define    pid_en_16_ALONE                    0
 #define    pid_en_16_SIGNED                   0
  #define           pid_en_16_off                              0
  #define           pid_en_16_enable                           1
 /* pid_en_17                      */
 #define    pid_en_17_ADDRESS                1302
 #define    pid_en_17_OFFSET                   1
 #define    pid_en_17_NBBIT                    1
 #define    pid_en_17_ALONE                    0
 #define    pid_en_17_SIGNED                   0
  #define           pid_en_17_off                              0
  #define           pid_en_17_enable                           1
 /* pid_en_18                      */
 #define    pid_en_18_ADDRESS                1302
 #define    pid_en_18_OFFSET                   2
 #define    pid_en_18_NBBIT                    1
 #define    pid_en_18_ALONE                    0
 #define    pid_en_18_SIGNED                   0
  #define           pid_en_18_off                              0
  #define           pid_en_18_enable                           1
 /* pid_en_19                      */
 #define    pid_en_19_ADDRESS                1302
 #define    pid_en_19_OFFSET                   3
 #define    pid_en_19_NBBIT                    1
 #define    pid_en_19_ALONE                    0
 #define    pid_en_19_SIGNED                   0
  #define           pid_en_19_off                              0
  #define           pid_en_19_enable                           1
 /* pid_en_20                      */
 #define    pid_en_20_ADDRESS                1302
 #define    pid_en_20_OFFSET                   4
 #define    pid_en_20_NBBIT                    1
 #define    pid_en_20_ALONE                    0
 #define    pid_en_20_SIGNED                   0
  #define           pid_en_20_off                              0
  #define           pid_en_20_enable                           1
 /* pid_en_21                      */
 #define    pid_en_21_ADDRESS                1302
 #define    pid_en_21_OFFSET                   5
 #define    pid_en_21_NBBIT                    1
 #define    pid_en_21_ALONE                    0
 #define    pid_en_21_SIGNED                   0
  #define           pid_en_21_off                              0
  #define           pid_en_21_enable                           1
 /* pid_en_22                      */
 #define    pid_en_22_ADDRESS                1302
 #define    pid_en_22_OFFSET                   6
 #define    pid_en_22_NBBIT                    1
 #define    pid_en_22_ALONE                    0
 #define    pid_en_22_SIGNED                   0
  #define           pid_en_22_off                              0
  #define           pid_en_22_enable                           1
 /* pid_en_23                      */
 #define    pid_en_23_ADDRESS                1302
 #define    pid_en_23_OFFSET                   7
 #define    pid_en_23_NBBIT                    1
 #define    pid_en_23_ALONE                    0
 #define    pid_en_23_SIGNED                   0
  #define           pid_en_23_off                              0
  #define           pid_en_23_enable                           1
 /* pid_en_24                      */
 #define    pid_en_24_ADDRESS                1303
 #define    pid_en_24_OFFSET                   0
 #define    pid_en_24_NBBIT                    1
 #define    pid_en_24_ALONE                    0
 #define    pid_en_24_SIGNED                   0
  #define           pid_en_24_off                              0
  #define           pid_en_24_enable                           1
 /* pid_en_25                      */
 #define    pid_en_25_ADDRESS                1303
 #define    pid_en_25_OFFSET                   1
 #define    pid_en_25_NBBIT                    1
 #define    pid_en_25_ALONE                    0
 #define    pid_en_25_SIGNED                   0
  #define           pid_en_25_off                              0
  #define           pid_en_25_enable                           1
 /* pid_en_26                      */
 #define    pid_en_26_ADDRESS                1303
 #define    pid_en_26_OFFSET                   2
 #define    pid_en_26_NBBIT                    1
 #define    pid_en_26_ALONE                    0
 #define    pid_en_26_SIGNED                   0
  #define           pid_en_26_off                              0
  #define           pid_en_26_enable                           1
 /* pid_en_27                      */
 #define    pid_en_27_ADDRESS                1303
 #define    pid_en_27_OFFSET                   3
 #define    pid_en_27_NBBIT                    1
 #define    pid_en_27_ALONE                    0
 #define    pid_en_27_SIGNED                   0
  #define           pid_en_27_off                              0
  #define           pid_en_27_enable                           1
 /* pid_en_28                      */
 #define    pid_en_28_ADDRESS                1303
 #define    pid_en_28_OFFSET                   4
 #define    pid_en_28_NBBIT                    1
 #define    pid_en_28_ALONE                    0
 #define    pid_en_28_SIGNED                   0
  #define           pid_en_28_off                              0
  #define           pid_en_28_enable                           1
 /* pid_en_29                      */
 #define    pid_en_29_ADDRESS                1303
 #define    pid_en_29_OFFSET                   5
 #define    pid_en_29_NBBIT                    1
 #define    pid_en_29_ALONE                    0
 #define    pid_en_29_SIGNED                   0
  #define           pid_en_29_off                              0
  #define           pid_en_29_enable                           1
 /* pid_en_30                      */
 #define    pid_en_30_ADDRESS                1303
 #define    pid_en_30_OFFSET                   6
 #define    pid_en_30_NBBIT                    1
 #define    pid_en_30_ALONE                    0
 #define    pid_en_30_SIGNED                   0
  #define           pid_en_30_off                              0
  #define           pid_en_30_enable                           1
 /* pid_en_31                      */
 #define    pid_en_31_ADDRESS                1303
 #define    pid_en_31_OFFSET                   7
 #define    pid_en_31_NBBIT                    1
 #define    pid_en_31_ALONE                    0
 #define    pid_en_31_SIGNED                   0
  #define           pid_en_31_off                              0
  #define           pid_en_31_enable                           1
 /* pid_0                          */
 #define    pid_0_ADDRESS                    1304
 #define    pid_0_OFFSET                       0
 #define    pid_0_NBBIT                       13
 #define    pid_0_ALONE                        1
 #define    pid_0_SIGNED                       0
 /* pid_1                          */
 #define    pid_1_ADDRESS                    1308
 #define    pid_1_OFFSET                       0
 #define    pid_1_NBBIT                       13
 #define    pid_1_ALONE                        1
 #define    pid_1_SIGNED                       0
 /* pid_2                          */
 #define    pid_2_ADDRESS                    1312
 #define    pid_2_OFFSET                       0
 #define    pid_2_NBBIT                       13
 #define    pid_2_ALONE                        1
 #define    pid_2_SIGNED                       0
 /* pid_3                          */
 #define    pid_3_ADDRESS                    1316
 #define    pid_3_OFFSET                       0
 #define    pid_3_NBBIT                       13
 #define    pid_3_ALONE                        1
 #define    pid_3_SIGNED                       0
 /* pid_4                          */
 #define    pid_4_ADDRESS                    1320
 #define    pid_4_OFFSET                       0
 #define    pid_4_NBBIT                       13
 #define    pid_4_ALONE                        1
 #define    pid_4_SIGNED                       0
 /* pid_5                          */
 #define    pid_5_ADDRESS                    1324
 #define    pid_5_OFFSET                       0
 #define    pid_5_NBBIT                       13
 #define    pid_5_ALONE                        1
 #define    pid_5_SIGNED                       0
 /* pid_6                          */
 #define    pid_6_ADDRESS                    1328
 #define    pid_6_OFFSET                       0
 #define    pid_6_NBBIT                       13
 #define    pid_6_ALONE                        1
 #define    pid_6_SIGNED                       0
 /* pid_7                          */
 #define    pid_7_ADDRESS                    1332
 #define    pid_7_OFFSET                       0
 #define    pid_7_NBBIT                       13
 #define    pid_7_ALONE                        1
 #define    pid_7_SIGNED                       0
 /* pid_8                          */
 #define    pid_8_ADDRESS                    1336
 #define    pid_8_OFFSET                       0
 #define    pid_8_NBBIT                       13
 #define    pid_8_ALONE                        1
 #define    pid_8_SIGNED                       0
 /* pid_9                          */
 #define    pid_9_ADDRESS                    1340
 #define    pid_9_OFFSET                       0
 #define    pid_9_NBBIT                       13
 #define    pid_9_ALONE                        1
 #define    pid_9_SIGNED                       0
 /* pid_10                         */
 #define    pid_10_ADDRESS                   1344
 #define    pid_10_OFFSET                      0
 #define    pid_10_NBBIT                      13
 #define    pid_10_ALONE                       1
 #define    pid_10_SIGNED                      0
 /* pid_11                         */
 #define    pid_11_ADDRESS                   1348
 #define    pid_11_OFFSET                      0
 #define    pid_11_NBBIT                      13
 #define    pid_11_ALONE                       1
 #define    pid_11_SIGNED                      0
 /* pid_12                         */
 #define    pid_12_ADDRESS                   1352
 #define    pid_12_OFFSET                      0
 #define    pid_12_NBBIT                      13
 #define    pid_12_ALONE                       1
 #define    pid_12_SIGNED                      0
 /* pid_13                         */
 #define    pid_13_ADDRESS                   1356
 #define    pid_13_OFFSET                      0
 #define    pid_13_NBBIT                      13
 #define    pid_13_ALONE                       1
 #define    pid_13_SIGNED                      0
 /* pid_14                         */
 #define    pid_14_ADDRESS                   1360
 #define    pid_14_OFFSET                      0
 #define    pid_14_NBBIT                      13
 #define    pid_14_ALONE                       1
 #define    pid_14_SIGNED                      0
 /* pid_15                         */
 #define    pid_15_ADDRESS                   1364
 #define    pid_15_OFFSET                      0
 #define    pid_15_NBBIT                      13
 #define    pid_15_ALONE                       1
 #define    pid_15_SIGNED                      0
 /* pid_16                         */
 #define    pid_16_ADDRESS                   1368
 #define    pid_16_OFFSET                      0
 #define    pid_16_NBBIT                      13
 #define    pid_16_ALONE                       1
 #define    pid_16_SIGNED                      0
 /* pid_17                         */
 #define    pid_17_ADDRESS                   1372
 #define    pid_17_OFFSET                      0
 #define    pid_17_NBBIT                      13
 #define    pid_17_ALONE                       1
 #define    pid_17_SIGNED                      0
 /* pid_18                         */
 #define    pid_18_ADDRESS                   1376
 #define    pid_18_OFFSET                      0
 #define    pid_18_NBBIT                      13
 #define    pid_18_ALONE                       1
 #define    pid_18_SIGNED                      0
 /* pid_19                         */
 #define    pid_19_ADDRESS                   1380
 #define    pid_19_OFFSET                      0
 #define    pid_19_NBBIT                      13
 #define    pid_19_ALONE                       1
 #define    pid_19_SIGNED                      0
 /* pid_20                         */
 #define    pid_20_ADDRESS                   1384
 #define    pid_20_OFFSET                      0
 #define    pid_20_NBBIT                      13
 #define    pid_20_ALONE                       1
 #define    pid_20_SIGNED                      0
 /* pid_21                         */
 #define    pid_21_ADDRESS                   1388
 #define    pid_21_OFFSET                      0
 #define    pid_21_NBBIT                      13
 #define    pid_21_ALONE                       1
 #define    pid_21_SIGNED                      0
 /* pid_22                         */
 #define    pid_22_ADDRESS                   1392
 #define    pid_22_OFFSET                      0
 #define    pid_22_NBBIT                      13
 #define    pid_22_ALONE                       1
 #define    pid_22_SIGNED                      0
 /* pid_23                         */
 #define    pid_23_ADDRESS                   1396
 #define    pid_23_OFFSET                      0
 #define    pid_23_NBBIT                      13
 #define    pid_23_ALONE                       1
 #define    pid_23_SIGNED                      0
 /* pid_24                         */
 #define    pid_24_ADDRESS                   1400
 #define    pid_24_OFFSET                      0
 #define    pid_24_NBBIT                      13
 #define    pid_24_ALONE                       1
 #define    pid_24_SIGNED                      0
 /* pid_25                         */
 #define    pid_25_ADDRESS                   1404
 #define    pid_25_OFFSET                      0
 #define    pid_25_NBBIT                      13
 #define    pid_25_ALONE                       1
 #define    pid_25_SIGNED                      0
 /* pid_26                         */
 #define    pid_26_ADDRESS                   1408
 #define    pid_26_OFFSET                      0
 #define    pid_26_NBBIT                      13
 #define    pid_26_ALONE                       1
 #define    pid_26_SIGNED                      0
 /* pid_27                         */
 #define    pid_27_ADDRESS                   1412
 #define    pid_27_OFFSET                      0
 #define    pid_27_NBBIT                      13
 #define    pid_27_ALONE                       1
 #define    pid_27_SIGNED                      0
 /* pid_28                         */
 #define    pid_28_ADDRESS                   1416
 #define    pid_28_OFFSET                      0
 #define    pid_28_NBBIT                      13
 #define    pid_28_ALONE                       1
 #define    pid_28_SIGNED                      0
 /* pid_29                         */
 #define    pid_29_ADDRESS                   1420
 #define    pid_29_OFFSET                      0
 #define    pid_29_NBBIT                      13
 #define    pid_29_ALONE                       1
 #define    pid_29_SIGNED                      0
 /* pid_30                         */
 #define    pid_30_ADDRESS                   1424
 #define    pid_30_OFFSET                      0
 #define    pid_30_NBBIT                      13
 #define    pid_30_ALONE                       1
 #define    pid_30_SIGNED                      0
 /* pid_31                         */
 #define    pid_31_ADDRESS                   1428
 #define    pid_31_OFFSET                      0
 #define    pid_31_NBBIT                      13
 #define    pid_31_ALONE                       1
 #define    pid_31_SIGNED                      0
 /* mode_scan                      */
 #define    mode_scan_ADDRESS                1440
 #define    mode_scan_OFFSET                   0
 #define    mode_scan_NBBIT                    1
 #define    mode_scan_ALONE                    0
 #define    mode_scan_SIGNED                   0
  #define           mode_scan_normal                           0
  #define           mode_scan_spectrum                         1
 /* scan_init                      */
 #define    scan_init_ADDRESS                1440
 #define    scan_init_OFFSET                   1
 #define    scan_init_NBBIT                    1
 #define    scan_init_ALONE                    0
 #define    scan_init_SIGNED                   0
 /* scan_power_read                */
 #define    scan_power_read_ADDRESS          1440
 #define    scan_power_read_OFFSET             2
 #define    scan_power_read_NBBIT              1
 #define    scan_power_read_ALONE              0
 #define    scan_power_read_SIGNED             0
 /* scan_sweep_range               */
 #define    scan_sweep_range_ADDRESS         1441
 #define    scan_sweep_range_OFFSET            0
 #define    scan_sweep_range_NBBIT             7
 #define    scan_sweep_range_ALONE             1
 #define    scan_sweep_range_SIGNED            0
 /* scan_sweep_step                */
 #define    scan_sweep_step_ADDRESS          1442
 #define    scan_sweep_step_OFFSET             0
 #define    scan_sweep_step_NBBIT              7
 #define    scan_sweep_step_ALONE              1
 #define    scan_sweep_step_SIGNED             0
 /* scan_alpha_iir                 */
 #define    scan_alpha_iir_ADDRESS           1443
 #define    scan_alpha_iir_OFFSET              0
 #define    scan_alpha_iir_NBBIT               5
 #define    scan_alpha_iir_ALONE               0
 #define    scan_alpha_iir_SIGNED              0
 /* scan_update_period             */
 #define    scan_update_period_ADDRESS       1443
 #define    scan_update_period_OFFSET          5
 #define    scan_update_period_NBBIT           2
 #define    scan_update_period_ALONE           0
 #define    scan_update_period_SIGNED          0
 /* scan_power                     */
 #define    scan_power_ADDRESS               1444
 #define    scan_power_OFFSET                  0
 #define    scan_power_NBBIT                  24
 #define    scan_power_ALONE                   1
 #define    scan_power_SIGNED                  0
 /* scan_power_ready               */
 #define    scan_power_ready_ADDRESS         1447
 #define    scan_power_ready_OFFSET            0
 #define    scan_power_ready_NBBIT             1
 #define    scan_power_ready_ALONE             0
 #define    scan_power_ready_SIGNED            0
  #define           scan_power_ready_busy                      0
  #define           scan_power_ready_ready                     1
 /* scan_sweep_end                 */
 #define    scan_sweep_end_ADDRESS           1447
 #define    scan_sweep_end_OFFSET              1
 #define    scan_sweep_end_NBBIT               1
 #define    scan_sweep_end_ALONE               0
 #define    scan_sweep_end_SIGNED              0
  #define           scan_sweep_end_busy                        0
  #define           scan_sweep_end_ready                       1
 /* gp0_deltasigma                 */
 #define    gp0_deltasigma_ADDRESS           1456
 #define    gp0_deltasigma_OFFSET              0
 #define    gp0_deltasigma_NBBIT               8
 #define    gp0_deltasigma_ALONE               1
 #define    gp0_deltasigma_SIGNED              0
 /* gp0_sel                        */
 #define    gp0_sel_ADDRESS                  1457
 #define    gp0_sel_OFFSET                     0
 #define    gp0_sel_NBBIT                      2
 #define    gp0_sel_ALONE                      0
 #define    gp0_sel_SIGNED                     0
  #define           gp0_sel_gp_o                               0
  #define           gp0_sel_interrupt                          1
  #define           gp0_sel_deltasigma                         2
  #define           gp0_sel_clock                              3
 /* gp0_p                          */
 #define    gp0_p_ADDRESS                    1457
 #define    gp0_p_OFFSET                       2
 #define    gp0_p_NBBIT                        1
 #define    gp0_p_ALONE                        0
 #define    gp0_p_SIGNED                       0
  #define           gp0_p_non_inverted                         0
  #define           gp0_p_inverted                             1
 /* gp0_t                          */
 #define    gp0_t_ADDRESS                    1457
 #define    gp0_t_OFFSET                       3
 #define    gp0_t_NBBIT                        1
 #define    gp0_t_ALONE                        0
 #define    gp0_t_SIGNED                       0
  #define           gp0_t_cmos                                 0
  #define           gp0_t_open_drain                           1
 /* gp0_en                         */
 #define    gp0_en_ADDRESS                   1457
 #define    gp0_en_OFFSET                      4
 #define    gp0_en_NBBIT                       1
 #define    gp0_en_ALONE                       0
 #define    gp0_en_SIGNED                      0
  #define           gp0_en_disable                             0
  #define           gp0_en_enable                              1
 /* gp0_o                          */
 #define    gp0_o_ADDRESS                    1457
 #define    gp0_o_OFFSET                       5
 #define    gp0_o_NBBIT                        1
 #define    gp0_o_ALONE                        0
 #define    gp0_o_SIGNED                       0
  #define           gp0_o_low                                  0
  #define           gp0_o_high                                 1
 /* gp0_i                          */
 #define    gp0_i_ADDRESS                    1460
 #define    gp0_i_OFFSET                       0
 #define    gp0_i_NBBIT                        1
 #define    gp0_i_ALONE                        1
 #define    gp0_i_SIGNED                       0
  #define           gp0_i_low                                  0
  #define           gp0_i_high                                 1
 /* fecl0_e                        */
 #define    fecl0_e_ADDRESS                  1462
 #define    fecl0_e_OFFSET                     0
 #define    fecl0_e_NBBIT                      1
 #define    fecl0_e_ALONE                      1
 #define    fecl0_e_SIGNED                     0
  #define           fecl0_e_disable                            0
  #define           fecl0_e_enable                             1
 /* fecl0_i                        */
 #define    fecl0_i_ADDRESS                  1466
 #define    fecl0_i_OFFSET                     0
 #define    fecl0_i_NBBIT                      1
 #define    fecl0_i_ALONE                      1
 #define    fecl0_i_SIGNED                     0
  #define           fecl0_i_unlocked                           0
  #define           fecl0_i_locked                             1
 /* rst_interrupt_gp0              */
 #define    rst_interrupt_gp0_ADDRESS        1468
 #define    rst_interrupt_gp0_OFFSET           0
 #define    rst_interrupt_gp0_NBBIT            1
 #define    rst_interrupt_gp0_ALONE            1
 #define    rst_interrupt_gp0_SIGNED           0
  #define           rst_interrupt_gp0_run                      0
  #define           rst_interrupt_gp0_reset                    1
 /* gpio0_tri                      */
 #define    gpio0_tri_ADDRESS                1473
 #define    gpio0_tri_OFFSET                   0
 #define    gpio0_tri_NBBIT                    1
 #define    gpio0_tri_ALONE                    1
 #define    gpio0_tri_SIGNED                   0
  #define           gpio0_tri_normal                           0
  #define           gpio0_tri_tristate                         1
 /* use_tx0                        */
 #define    use_tx0_ADDRESS                  1474
 #define    use_tx0_OFFSET                     0
 #define    use_tx0_NBBIT                      1
 #define    use_tx0_ALONE                      0
 #define    use_tx0_SIGNED                     0
  #define           use_tx0_no                                 0
  #define           use_tx0_yes                                1
 /* use_rx0                        */
 #define    use_rx0_ADDRESS                  1474
 #define    use_rx0_OFFSET                     1
 #define    use_rx0_NBBIT                      1
 #define    use_rx0_ALONE                      0
 #define    use_rx0_SIGNED                     0
  #define           use_rx0_no                                 0
  #define           use_rx0_yes                                1
 /* demodlt0_e                     */
 #define    demodlt0_e_ADDRESS               1476
 #define    demodlt0_e_OFFSET                  0
 #define    demodlt0_e_NBBIT                   1
 #define    demodlt0_e_ALONE                   0
 #define    demodlt0_e_SIGNED                  0
  #define           demodlt0_e_disable                         0
  #define           demodlt0_e_enable                          1
 /* demodlc0_e                     */
 #define    demodlc0_e_ADDRESS               1476
 #define    demodlc0_e_OFFSET                  1
 #define    demodlc0_e_NBBIT                   1
 #define    demodlc0_e_ALONE                   0
 #define    demodlc0_e_SIGNED                  0
  #define           demodlc0_e_disable                         0
  #define           demodlc0_e_enable                          1
 /* freql0_e                       */
 #define    freql0_e_ADDRESS                 1476
 #define    freql0_e_OFFSET                    2
 #define    freql0_e_NBBIT                     1
 #define    freql0_e_ALONE                     0
 #define    freql0_e_SIGNED                    0
  #define           freql0_e_disable                           0
  #define           freql0_e_enable                            1
 /* timel0_e                       */
 #define    timel0_e_ADDRESS                 1476
 #define    timel0_e_OFFSET                    3
 #define    timel0_e_NBBIT                     1
 #define    timel0_e_ALONE                     0
 #define    timel0_e_SIGNED                    0
  #define           timel0_e_disable                           0
  #define           timel0_e_enable                            1
 /* tpsl0_e                        */
 #define    tpsl0_e_ADDRESS                  1476
 #define    tpsl0_e_OFFSET                     4
 #define    tpsl0_e_NBBIT                      1
 #define    tpsl0_e_ALONE                      0
 #define    tpsl0_e_SIGNED                     0
  #define           tpsl0_e_disable                            0
  #define           tpsl0_e_enable                             1
 /* fftl0_e                        */
 #define    fftl0_e_ADDRESS                  1476
 #define    fftl0_e_OFFSET                     5
 #define    fftl0_e_NBBIT                      1
 #define    fftl0_e_ALONE                      0
 #define    fftl0_e_SIGNED                     0
  #define           fftl0_e_disable                            0
  #define           fftl0_e_enable                             1
 /* agcl0_e                        */
 #define    agcl0_e_ADDRESS                  1477
 #define    agcl0_e_OFFSET                     0
 #define    agcl0_e_NBBIT                      1
 #define    agcl0_e_ALONE                      0
 #define    agcl0_e_SIGNED                     0
  #define           agcl0_e_disable                            0
  #define           agcl0_e_enable                             1
 /* aafl0_e                        */
 #define    aafl0_e_ADDRESS                  1477
 #define    aafl0_e_OFFSET                     1
 #define    aafl0_e_NBBIT                      1
 #define    aafl0_e_ALONE                      0
 #define    aafl0_e_SIGNED                     0
  #define           aafl0_e_disable                            0
  #define           aafl0_e_enable                             1
 /* acil0_e                        */
 #define    acil0_e_ADDRESS                  1477
 #define    acil0_e_OFFSET                     2
 #define    acil0_e_NBBIT                      1
 #define    acil0_e_ALONE                      0
 #define    acil0_e_SIGNED                     0
  #define           acil0_e_disable                            0
  #define           acil0_e_enable                             1
 /* correll0_e                     */
 #define    correll0_e_ADDRESS               1477
 #define    correll0_e_OFFSET                  3
 #define    correll0_e_NBBIT                   1
 #define    correll0_e_ALONE                   0
 #define    correll0_e_SIGNED                  0
  #define           correll0_e_disable                         0
  #define           correll0_e_enable                          1
 /* psl0_e                         */
 #define    psl0_e_ADDRESS                   1477
 #define    psl0_e_OFFSET                      4
 #define    psl0_e_NBBIT                       1
 #define    psl0_e_ALONE                       0
 #define    psl0_e_SIGNED                      0
  #define           psl0_e_disable                             0
  #define           psl0_e_enable                              1
 /* wde0_e                         */
 #define    wde0_e_ADDRESS                   1477
 #define    wde0_e_OFFSET                      5
 #define    wde0_e_NBBIT                       1
 #define    wde0_e_ALONE                       0
 #define    wde0_e_SIGNED                      0
  #define           wde0_e_disable                             0
  #define           wde0_e_enable                              1
 /* trape0_e                       */
 #define    trape0_e_ADDRESS                 1477
 #define    trape0_e_OFFSET                    6
 #define    trape0_e_NBBIT                     1
 #define    trape0_e_ALONE                     0
 #define    trape0_e_SIGNED                    0
  #define           trape0_e_disable                           0
  #define           trape0_e_enable                            1
 /* demodlt0_i                     */
 #define    demodlt0_i_ADDRESS               1480
 #define    demodlt0_i_OFFSET                  0
 #define    demodlt0_i_NBBIT                   1
 #define    demodlt0_i_ALONE                   0
 #define    demodlt0_i_SIGNED                  0
  #define           demodlt0_i_unlocked                        0
  #define           demodlt0_i_locked                          1
 /* demodlc0_i                     */
 #define    demodlc0_i_ADDRESS               1480
 #define    demodlc0_i_OFFSET                  1
 #define    demodlc0_i_NBBIT                   1
 #define    demodlc0_i_ALONE                   0
 #define    demodlc0_i_SIGNED                  0
  #define           demodlc0_i_unlocked                        0
  #define           demodlc0_i_locked                          1
 /* freql0_i                       */
 #define    freql0_i_ADDRESS                 1480
 #define    freql0_i_OFFSET                    2
 #define    freql0_i_NBBIT                     1
 #define    freql0_i_ALONE                     0
 #define    freql0_i_SIGNED                    0
  #define           freql0_i_unlocked                          0
  #define           freql0_i_locked                            1
 /* timel0_i                       */
 #define    timel0_i_ADDRESS                 1480
 #define    timel0_i_OFFSET                    3
 #define    timel0_i_NBBIT                     1
 #define    timel0_i_ALONE                     0
 #define    timel0_i_SIGNED                    0
  #define           timel0_i_unlocked                          0
  #define           timel0_i_locked                            1
 /* tpsl0_i                        */
 #define    tpsl0_i_ADDRESS                  1480
 #define    tpsl0_i_OFFSET                     4
 #define    tpsl0_i_NBBIT                      1
 #define    tpsl0_i_ALONE                      0
 #define    tpsl0_i_SIGNED                     0
  #define           tpsl0_i_unlocked                           0
  #define           tpsl0_i_locked                             1
 /* fftl0_i                        */
 #define    fftl0_i_ADDRESS                  1480
 #define    fftl0_i_OFFSET                     5
 #define    fftl0_i_NBBIT                      1
 #define    fftl0_i_ALONE                      0
 #define    fftl0_i_SIGNED                     0
  #define           fftl0_i_unlocked                           0
  #define           fftl0_i_locked                             1
 /* agcl0_i                        */
 #define    agcl0_i_ADDRESS                  1480
 #define    agcl0_i_OFFSET                     6
 #define    agcl0_i_NBBIT                      1
 #define    agcl0_i_ALONE                      0
 #define    agcl0_i_SIGNED                     0
  #define           agcl0_i_unlocked                           0
  #define           agcl0_i_locked                             1
 /* aafl0_i                        */
 #define    aafl0_i_ADDRESS                  1481
 #define    aafl0_i_OFFSET                     0
 #define    aafl0_i_NBBIT                      1
 #define    aafl0_i_ALONE                      0
 #define    aafl0_i_SIGNED                     0
  #define           aafl0_i_unlocked                           0
  #define           aafl0_i_locked                             1
 /* acil0_i                        */
 #define    acil0_i_ADDRESS                  1481
 #define    acil0_i_OFFSET                     1
 #define    acil0_i_NBBIT                      1
 #define    acil0_i_ALONE                      0
 #define    acil0_i_SIGNED                     0
  #define           acil0_i_unlocked                           0
  #define           acil0_i_locked                             1
 /* correll0_i                     */
 #define    correll0_i_ADDRESS               1481
 #define    correll0_i_OFFSET                  2
 #define    correll0_i_NBBIT                   1
 #define    correll0_i_ALONE                   0
 #define    correll0_i_SIGNED                  0
  #define           correll0_i_unlocked                        0
  #define           correll0_i_locked                          1
 /* psl0_i                         */
 #define    psl0_i_ADDRESS                   1481
 #define    psl0_i_OFFSET                      3
 #define    psl0_i_NBBIT                       1
 #define    psl0_i_ALONE                       0
 #define    psl0_i_SIGNED                      0
  #define           psl0_i_unlocked                            0
  #define           psl0_i_locked                              1
 /* wde0_i                         */
 #define    wde0_i_ADDRESS                   1481
 #define    wde0_i_OFFSET                      4
 #define    wde0_i_NBBIT                       1
 #define    wde0_i_ALONE                       0
 #define    wde0_i_SIGNED                      0
  #define           wde0_i_no_error                            0
  #define           wde0_i_error                               1
 /* trape0_i                       */
 #define    trape0_i_ADDRESS                 1481
 #define    trape0_i_OFFSET                    5
 #define    trape0_i_NBBIT                     1
 #define    trape0_i_ALONE                     0
 #define    trape0_i_SIGNED                    0
  #define           trape0_i_no_error                          0
  #define           trape0_i_error                             1
 /* gpio0_slr                      */
 #define    gpio0_slr_ADDRESS                1482
 #define    gpio0_slr_OFFSET                   0
 #define    gpio0_slr_NBBIT                    2
 #define    gpio0_slr_ALONE                    1
 #define    gpio0_slr_SIGNED                   0
  #define           gpio0_slr_fastest edges                    0
  #define           gpio0_slr_slowest edges                    1
  #define           gpio0_slr_moderate edges                   2
  #define           gpio0_slr_fast edges                       3
 /* gp1_deltasigma                 */
 #define    gp1_deltasigma_ADDRESS           1488
 #define    gp1_deltasigma_OFFSET              0
 #define    gp1_deltasigma_NBBIT               8
 #define    gp1_deltasigma_ALONE               1
 #define    gp1_deltasigma_SIGNED              0
 /* gp1_sel                        */
 #define    gp1_sel_ADDRESS                  1489
 #define    gp1_sel_OFFSET                     0
 #define    gp1_sel_NBBIT                      2
 #define    gp1_sel_ALONE                      0
 #define    gp1_sel_SIGNED                     0
  #define           gp1_sel_gp_o                               0
  #define           gp1_sel_interrupt                          1
  #define           gp1_sel_deltasigma                         2
  #define           gp1_sel_clock                              3
 /* gp1_p                          */
 #define    gp1_p_ADDRESS                    1489
 #define    gp1_p_OFFSET                       2
 #define    gp1_p_NBBIT                        1
 #define    gp1_p_ALONE                        0
 #define    gp1_p_SIGNED                       0
  #define           gp1_p_non_inverted                         0
  #define           gp1_p_inverted                             1
 /* gp1_t                          */
 #define    gp1_t_ADDRESS                    1489
 #define    gp1_t_OFFSET                       3
 #define    gp1_t_NBBIT                        1
 #define    gp1_t_ALONE                        0
 #define    gp1_t_SIGNED                       0
  #define           gp1_t_cmos                                 0
  #define           gp1_t_open_drain                           1
 /* gp1_en                         */
 #define    gp1_en_ADDRESS                   1489
 #define    gp1_en_OFFSET                      4
 #define    gp1_en_NBBIT                       1
 #define    gp1_en_ALONE                       0
 #define    gp1_en_SIGNED                      0
  #define           gp1_en_disable                             0
  #define           gp1_en_enable                              1
 /* gp1_o                          */
 #define    gp1_o_ADDRESS                    1489
 #define    gp1_o_OFFSET                       5
 #define    gp1_o_NBBIT                        1
 #define    gp1_o_ALONE                        0
 #define    gp1_o_SIGNED                       0
  #define           gp1_o_low                                  0
  #define           gp1_o_high                                 1
 /* gp1_i                          */
 #define    gp1_i_ADDRESS                    1492
 #define    gp1_i_OFFSET                       0
 #define    gp1_i_NBBIT                        1
 #define    gp1_i_ALONE                        1
 #define    gp1_i_SIGNED                       0
  #define           gp1_i_low                                  0
  #define           gp1_i_high                                 1
 /* fecl1_e                        */
 #define    fecl1_e_ADDRESS                  1494
 #define    fecl1_e_OFFSET                     0
 #define    fecl1_e_NBBIT                      1
 #define    fecl1_e_ALONE                      1
 #define    fecl1_e_SIGNED                     0
  #define           fecl1_e_disable                            0
  #define           fecl1_e_enable                             1
 /* fecl1_i                        */
 #define    fecl1_i_ADDRESS                  1498
 #define    fecl1_i_OFFSET                     0
 #define    fecl1_i_NBBIT                      1
 #define    fecl1_i_ALONE                      1
 #define    fecl1_i_SIGNED                     0
  #define           fecl1_i_unlocked                           0
  #define           fecl1_i_locked                             1
 /* rst_interrupt_gp1              */
 #define    rst_interrupt_gp1_ADDRESS        1500
 #define    rst_interrupt_gp1_OFFSET           0
 #define    rst_interrupt_gp1_NBBIT            1
 #define    rst_interrupt_gp1_ALONE            1
 #define    rst_interrupt_gp1_SIGNED           0
  #define           rst_interrupt_gp1_run                      0
  #define           rst_interrupt_gp1_reset                    1
 /* use_tx1                        */
 #define    use_tx1_ADDRESS                  1506
 #define    use_tx1_OFFSET                     0
 #define    use_tx1_NBBIT                      1
 #define    use_tx1_ALONE                      0
 #define    use_tx1_SIGNED                     0
  #define           use_tx1_no                                 0
  #define           use_tx1_yes                                1
 /* use_rx1                        */
 #define    use_rx1_ADDRESS                  1506
 #define    use_rx1_OFFSET                     1
 #define    use_rx1_NBBIT                      1
 #define    use_rx1_ALONE                      0
 #define    use_rx1_SIGNED                     0
  #define           use_rx1_no                                 0
  #define           use_rx1_yes                                1
 /* demodlt1_e                     */
 #define    demodlt1_e_ADDRESS               1508
 #define    demodlt1_e_OFFSET                  0
 #define    demodlt1_e_NBBIT                   1
 #define    demodlt1_e_ALONE                   0
 #define    demodlt1_e_SIGNED                  0
  #define           demodlt1_e_disable                         0
  #define           demodlt1_e_enable                          1
 /* demodlc1_e                     */
 #define    demodlc1_e_ADDRESS               1508
 #define    demodlc1_e_OFFSET                  1
 #define    demodlc1_e_NBBIT                   1
 #define    demodlc1_e_ALONE                   0
 #define    demodlc1_e_SIGNED                  0
  #define           demodlc1_e_disable                         0
  #define           demodlc1_e_enable                          1
 /* freql1_e                       */
 #define    freql1_e_ADDRESS                 1508
 #define    freql1_e_OFFSET                    2
 #define    freql1_e_NBBIT                     1
 #define    freql1_e_ALONE                     0
 #define    freql1_e_SIGNED                    0
  #define           freql1_e_disable                           0
  #define           freql1_e_enable                            1
 /* timel1_e                       */
 #define    timel1_e_ADDRESS                 1508
 #define    timel1_e_OFFSET                    3
 #define    timel1_e_NBBIT                     1
 #define    timel1_e_ALONE                     0
 #define    timel1_e_SIGNED                    0
  #define           timel1_e_disable                           0
  #define           timel1_e_enable                            1
 /* tpsl1_e                        */
 #define    tpsl1_e_ADDRESS                  1508
 #define    tpsl1_e_OFFSET                     4
 #define    tpsl1_e_NBBIT                      1
 #define    tpsl1_e_ALONE                      0
 #define    tpsl1_e_SIGNED                     0
  #define           tpsl1_e_disable                            0
  #define           tpsl1_e_enable                             1
 /* fftl1_e                        */
 #define    fftl1_e_ADDRESS                  1508
 #define    fftl1_e_OFFSET                     5
 #define    fftl1_e_NBBIT                      1
 #define    fftl1_e_ALONE                      0
 #define    fftl1_e_SIGNED                     0
  #define           fftl1_e_disable                            0
  #define           fftl1_e_enable                             1
 /* agcl1_e                        */
 #define    agcl1_e_ADDRESS                  1509
 #define    agcl1_e_OFFSET                     0
 #define    agcl1_e_NBBIT                      1
 #define    agcl1_e_ALONE                      0
 #define    agcl1_e_SIGNED                     0
  #define           agcl1_e_disable                            0
  #define           agcl1_e_enable                             1
 /* aafl1_e                        */
 #define    aafl1_e_ADDRESS                  1509
 #define    aafl1_e_OFFSET                     1
 #define    aafl1_e_NBBIT                      1
 #define    aafl1_e_ALONE                      0
 #define    aafl1_e_SIGNED                     0
  #define           aafl1_e_disable                            0
  #define           aafl1_e_enable                             1
 /* acil1_e                        */
 #define    acil1_e_ADDRESS                  1509
 #define    acil1_e_OFFSET                     2
 #define    acil1_e_NBBIT                      1
 #define    acil1_e_ALONE                      0
 #define    acil1_e_SIGNED                     0
  #define           acil1_e_disable                            0
  #define           acil1_e_enable                             1
 /* correll1_e                     */
 #define    correll1_e_ADDRESS               1509
 #define    correll1_e_OFFSET                  3
 #define    correll1_e_NBBIT                   1
 #define    correll1_e_ALONE                   0
 #define    correll1_e_SIGNED                  0
  #define           correll1_e_disable                         0
  #define           correll1_e_enable                          1
 /* psl1_e                         */
 #define    psl1_e_ADDRESS                   1509
 #define    psl1_e_OFFSET                      4
 #define    psl1_e_NBBIT                       1
 #define    psl1_e_ALONE                       0
 #define    psl1_e_SIGNED                      0
  #define           psl1_e_disable                             0
  #define           psl1_e_enable                              1
 /* wde1_e                         */
 #define    wde1_e_ADDRESS                   1509
 #define    wde1_e_OFFSET                      5
 #define    wde1_e_NBBIT                       1
 #define    wde1_e_ALONE                       0
 #define    wde1_e_SIGNED                      0
  #define           wde1_e_disable                             0
  #define           wde1_e_enable                              1
 /* trape1_e                       */
 #define    trape1_e_ADDRESS                 1509
 #define    trape1_e_OFFSET                    6
 #define    trape1_e_NBBIT                     1
 #define    trape1_e_ALONE                     0
 #define    trape1_e_SIGNED                    0
  #define           trape1_e_disable                           0
  #define           trape1_e_enable                            1
 /* demodlt1_i                     */
 #define    demodlt1_i_ADDRESS               1512
 #define    demodlt1_i_OFFSET                  0
 #define    demodlt1_i_NBBIT                   1
 #define    demodlt1_i_ALONE                   0
 #define    demodlt1_i_SIGNED                  0
  #define           demodlt1_i_unlocked                        0
  #define           demodlt1_i_locked                          1
 /* demodlc1_i                     */
 #define    demodlc1_i_ADDRESS               1512
 #define    demodlc1_i_OFFSET                  1
 #define    demodlc1_i_NBBIT                   1
 #define    demodlc1_i_ALONE                   0
 #define    demodlc1_i_SIGNED                  0
  #define           demodlc1_i_unlocked                        0
  #define           demodlc1_i_locked                          1
 /* freql1_i                       */
 #define    freql1_i_ADDRESS                 1512
 #define    freql1_i_OFFSET                    2
 #define    freql1_i_NBBIT                     1
 #define    freql1_i_ALONE                     0
 #define    freql1_i_SIGNED                    0
  #define           freql1_i_unlocked                          0
  #define           freql1_i_locked                            1
 /* timel1_i                       */
 #define    timel1_i_ADDRESS                 1512
 #define    timel1_i_OFFSET                    3
 #define    timel1_i_NBBIT                     1
 #define    timel1_i_ALONE                     0
 #define    timel1_i_SIGNED                    0
  #define           timel1_i_unlocked                          0
  #define           timel1_i_locked                            1
 /* tpsl1_i                        */
 #define    tpsl1_i_ADDRESS                  1512
 #define    tpsl1_i_OFFSET                     4
 #define    tpsl1_i_NBBIT                      1
 #define    tpsl1_i_ALONE                      0
 #define    tpsl1_i_SIGNED                     0
  #define           tpsl1_i_unlocked                           0
  #define           tpsl1_i_locked                             1
 /* fftl1_i                        */
 #define    fftl1_i_ADDRESS                  1512
 #define    fftl1_i_OFFSET                     5
 #define    fftl1_i_NBBIT                      1
 #define    fftl1_i_ALONE                      0
 #define    fftl1_i_SIGNED                     0
  #define           fftl1_i_unlocked                           0
  #define           fftl1_i_locked                             1
 /* agcl1_i                        */
 #define    agcl1_i_ADDRESS                  1512
 #define    agcl1_i_OFFSET                     6
 #define    agcl1_i_NBBIT                      1
 #define    agcl1_i_ALONE                      0
 #define    agcl1_i_SIGNED                     0
  #define           agcl1_i_unlocked                           0
  #define           agcl1_i_locked                             1
 /* aafl1_i                        */
 #define    aafl1_i_ADDRESS                  1513
 #define    aafl1_i_OFFSET                     0
 #define    aafl1_i_NBBIT                      1
 #define    aafl1_i_ALONE                      0
 #define    aafl1_i_SIGNED                     0
  #define           aafl1_i_unlocked                           0
  #define           aafl1_i_locked                             1
 /* acil1_i                        */
 #define    acil1_i_ADDRESS                  1513
 #define    acil1_i_OFFSET                     1
 #define    acil1_i_NBBIT                      1
 #define    acil1_i_ALONE                      0
 #define    acil1_i_SIGNED                     0
  #define           acil1_i_unlocked                           0
  #define           acil1_i_locked                             1
 /* correll1_i                     */
 #define    correll1_i_ADDRESS               1513
 #define    correll1_i_OFFSET                  2
 #define    correll1_i_NBBIT                   1
 #define    correll1_i_ALONE                   0
 #define    correll1_i_SIGNED                  0
  #define           correll1_i_unlocked                        0
  #define           correll1_i_locked                          1
 /* psl1_i                         */
 #define    psl1_i_ADDRESS                   1513
 #define    psl1_i_OFFSET                      3
 #define    psl1_i_NBBIT                       1
 #define    psl1_i_ALONE                       0
 #define    psl1_i_SIGNED                      0
  #define           psl1_i_unlocked                            0
  #define           psl1_i_locked                              1
 /* wde1_i                         */
 #define    wde1_i_ADDRESS                   1513
 #define    wde1_i_OFFSET                      4
 #define    wde1_i_NBBIT                       1
 #define    wde1_i_ALONE                       0
 #define    wde1_i_SIGNED                      0
  #define           wde1_i_no_error                            0
  #define           wde1_i_error                               1
 /* trape1_i                       */
 #define    trape1_i_ADDRESS                 1513
 #define    trape1_i_OFFSET                    5
 #define    trape1_i_NBBIT                     1
 #define    trape1_i_ALONE                     0
 #define    trape1_i_SIGNED                    0
  #define           trape1_i_no_error                          0
  #define           trape1_i_error                             1
 /* gp2_deltasigma                 */
 #define    gp2_deltasigma_ADDRESS           1520
 #define    gp2_deltasigma_OFFSET              0
 #define    gp2_deltasigma_NBBIT               8
 #define    gp2_deltasigma_ALONE               1
 #define    gp2_deltasigma_SIGNED              0
 /* gp2_sel                        */
 #define    gp2_sel_ADDRESS                  1521
 #define    gp2_sel_OFFSET                     0
 #define    gp2_sel_NBBIT                      2
 #define    gp2_sel_ALONE                      0
 #define    gp2_sel_SIGNED                     0
  #define           gp2_sel_gp_o                               0
  #define           gp2_sel_interrupt                          1
  #define           gp2_sel_deltasigma                         2
  #define           gp2_sel_clock                              3
 /* gp2_p                          */
 #define    gp2_p_ADDRESS                    1521
 #define    gp2_p_OFFSET                       2
 #define    gp2_p_NBBIT                        1
 #define    gp2_p_ALONE                        0
 #define    gp2_p_SIGNED                       0
  #define           gp2_p_non_inverted                         0
  #define           gp2_p_inverted                             1
 /* gp2_t                          */
 #define    gp2_t_ADDRESS                    1521
 #define    gp2_t_OFFSET                       3
 #define    gp2_t_NBBIT                        1
 #define    gp2_t_ALONE                        0
 #define    gp2_t_SIGNED                       0
  #define           gp2_t_cmos                                 0
  #define           gp2_t_open_drain                           1
 /* gp2_en                         */
 #define    gp2_en_ADDRESS                   1521
 #define    gp2_en_OFFSET                      4
 #define    gp2_en_NBBIT                       1
 #define    gp2_en_ALONE                       0
 #define    gp2_en_SIGNED                      0
  #define           gp2_en_disable                             0
  #define           gp2_en_enable                              1
 /* gp2_o                          */
 #define    gp2_o_ADDRESS                    1521
 #define    gp2_o_OFFSET                       5
 #define    gp2_o_NBBIT                        1
 #define    gp2_o_ALONE                        0
 #define    gp2_o_SIGNED                       0
  #define           gp2_o_low                                  0
  #define           gp2_o_high                                 1
 /* gp2_i                          */
 #define    gp2_i_ADDRESS                    1524
 #define    gp2_i_OFFSET                       0
 #define    gp2_i_NBBIT                        1
 #define    gp2_i_ALONE                        1
 #define    gp2_i_SIGNED                       0
  #define           gp2_i_low                                  0
  #define           gp2_i_high                                 1
 /* fecl2_e                        */
 #define    fecl2_e_ADDRESS                  1526
 #define    fecl2_e_OFFSET                     0
 #define    fecl2_e_NBBIT                      1
 #define    fecl2_e_ALONE                      1
 #define    fecl2_e_SIGNED                     0
  #define           fecl2_e_disable                            0
  #define           fecl2_e_enable                             1
 /* fecl2_i                        */
 #define    fecl2_i_ADDRESS                  1530
 #define    fecl2_i_OFFSET                     0
 #define    fecl2_i_NBBIT                      1
 #define    fecl2_i_ALONE                      1
 #define    fecl2_i_SIGNED                     0
  #define           fecl2_i_unlocked                           0
  #define           fecl2_i_locked                             1
 /* rst_interrupt_gp2              */
 #define    rst_interrupt_gp2_ADDRESS        1536
 #define    rst_interrupt_gp2_OFFSET           0
 #define    rst_interrupt_gp2_NBBIT            1
 #define    rst_interrupt_gp2_ALONE            1
 #define    rst_interrupt_gp2_SIGNED           0
  #define           rst_interrupt_gp2_run                      0
  #define           rst_interrupt_gp2_reset                    1
 /* use_tx2                        */
 #define    use_tx2_ADDRESS                  1542
 #define    use_tx2_OFFSET                     0
 #define    use_tx2_NBBIT                      1
 #define    use_tx2_ALONE                      0
 #define    use_tx2_SIGNED                     0
  #define           use_tx2_no                                 0
  #define           use_tx2_yes                                1
 /* use_rx2                        */
 #define    use_rx2_ADDRESS                  1542
 #define    use_rx2_OFFSET                     1
 #define    use_rx2_NBBIT                      1
 #define    use_rx2_ALONE                      0
 #define    use_rx2_SIGNED                     0
  #define           use_rx2_no                                 0
  #define           use_rx2_yes                                1
 /* demodlt2_e                     */
 #define    demodlt2_e_ADDRESS               1544
 #define    demodlt2_e_OFFSET                  0
 #define    demodlt2_e_NBBIT                   1
 #define    demodlt2_e_ALONE                   0
 #define    demodlt2_e_SIGNED                  0
  #define           demodlt2_e_disable                         0
  #define           demodlt2_e_enable                          1
 /* demodlc2_e                     */
 #define    demodlc2_e_ADDRESS               1544
 #define    demodlc2_e_OFFSET                  1
 #define    demodlc2_e_NBBIT                   1
 #define    demodlc2_e_ALONE                   0
 #define    demodlc2_e_SIGNED                  0
  #define           demodlc2_e_disable                         0
  #define           demodlc2_e_enable                          1
 /* freql2_e                       */
 #define    freql2_e_ADDRESS                 1544
 #define    freql2_e_OFFSET                    2
 #define    freql2_e_NBBIT                     1
 #define    freql2_e_ALONE                     0
 #define    freql2_e_SIGNED                    0
  #define           freql2_e_disable                           0
  #define           freql2_e_enable                            1
 /* timel2_e                       */
 #define    timel2_e_ADDRESS                 1544
 #define    timel2_e_OFFSET                    3
 #define    timel2_e_NBBIT                     1
 #define    timel2_e_ALONE                     0
 #define    timel2_e_SIGNED                    0
  #define           timel2_e_disable                           0
  #define           timel2_e_enable                            1
 /* tpsl2_e                        */
 #define    tpsl2_e_ADDRESS                  1544
 #define    tpsl2_e_OFFSET                     4
 #define    tpsl2_e_NBBIT                      1
 #define    tpsl2_e_ALONE                      0
 #define    tpsl2_e_SIGNED                     0
  #define           tpsl2_e_disable                            0
  #define           tpsl2_e_enable                             1
 /* fftl2_e                        */
 #define    fftl2_e_ADDRESS                  1544
 #define    fftl2_e_OFFSET                     5
 #define    fftl2_e_NBBIT                      1
 #define    fftl2_e_ALONE                      0
 #define    fftl2_e_SIGNED                     0
  #define           fftl2_e_disable                            0
  #define           fftl2_e_enable                             1
 /* agcl2_e                        */
 #define    agcl2_e_ADDRESS                  1545
 #define    agcl2_e_OFFSET                     0
 #define    agcl2_e_NBBIT                      1
 #define    agcl2_e_ALONE                      0
 #define    agcl2_e_SIGNED                     0
  #define           agcl2_e_disable                            0
  #define           agcl2_e_enable                             1
 /* aafl2_e                        */
 #define    aafl2_e_ADDRESS                  1545
 #define    aafl2_e_OFFSET                     1
 #define    aafl2_e_NBBIT                      1
 #define    aafl2_e_ALONE                      0
 #define    aafl2_e_SIGNED                     0
  #define           aafl2_e_disable                            0
  #define           aafl2_e_enable                             1
 /* acil2_e                        */
 #define    acil2_e_ADDRESS                  1545
 #define    acil2_e_OFFSET                     2
 #define    acil2_e_NBBIT                      1
 #define    acil2_e_ALONE                      0
 #define    acil2_e_SIGNED                     0
  #define           acil2_e_disable                            0
  #define           acil2_e_enable                             1
 /* correll2_e                     */
 #define    correll2_e_ADDRESS               1545
 #define    correll2_e_OFFSET                  3
 #define    correll2_e_NBBIT                   1
 #define    correll2_e_ALONE                   0
 #define    correll2_e_SIGNED                  0
  #define           correll2_e_disable                         0
  #define           correll2_e_enable                          1
 /* psl2_e                         */
 #define    psl2_e_ADDRESS                   1545
 #define    psl2_e_OFFSET                      4
 #define    psl2_e_NBBIT                       1
 #define    psl2_e_ALONE                       0
 #define    psl2_e_SIGNED                      0
  #define           psl2_e_disable                             0
  #define           psl2_e_enable                              1
 /* wde2_e                         */
 #define    wde2_e_ADDRESS                   1545
 #define    wde2_e_OFFSET                      5
 #define    wde2_e_NBBIT                       1
 #define    wde2_e_ALONE                       0
 #define    wde2_e_SIGNED                      0
  #define           wde2_e_disable                             0
  #define           wde2_e_enable                              1
 /* trape2_e                       */
 #define    trape2_e_ADDRESS                 1545
 #define    trape2_e_OFFSET                    6
 #define    trape2_e_NBBIT                     1
 #define    trape2_e_ALONE                     0
 #define    trape2_e_SIGNED                    0
  #define           trape2_e_disable                           0
  #define           trape2_e_enable                            1
 /* demodlt2_i                     */
 #define    demodlt2_i_ADDRESS               1548
 #define    demodlt2_i_OFFSET                  0
 #define    demodlt2_i_NBBIT                   1
 #define    demodlt2_i_ALONE                   0
 #define    demodlt2_i_SIGNED                  0
  #define           demodlt2_i_unlocked                        0
  #define           demodlt2_i_locked                          1
 /* demodlc2_i                     */
 #define    demodlc2_i_ADDRESS               1548
 #define    demodlc2_i_OFFSET                  1
 #define    demodlc2_i_NBBIT                   1
 #define    demodlc2_i_ALONE                   0
 #define    demodlc2_i_SIGNED                  0
  #define           demodlc2_i_unlocked                        0
  #define           demodlc2_i_locked                          1
 /* freql2_i                       */
 #define    freql2_i_ADDRESS                 1548
 #define    freql2_i_OFFSET                    2
 #define    freql2_i_NBBIT                     1
 #define    freql2_i_ALONE                     0
 #define    freql2_i_SIGNED                    0
  #define           freql2_i_unlocked                          0
  #define           freql2_i_locked                            1
 /* timel2_i                       */
 #define    timel2_i_ADDRESS                 1548
 #define    timel2_i_OFFSET                    3
 #define    timel2_i_NBBIT                     1
 #define    timel2_i_ALONE                     0
 #define    timel2_i_SIGNED                    0
  #define           timel2_i_unlocked                          0
  #define           timel2_i_locked                            1
 /* tpsl2_i                        */
 #define    tpsl2_i_ADDRESS                  1548
 #define    tpsl2_i_OFFSET                     4
 #define    tpsl2_i_NBBIT                      1
 #define    tpsl2_i_ALONE                      0
 #define    tpsl2_i_SIGNED                     0
  #define           tpsl2_i_unlocked                           0
  #define           tpsl2_i_locked                             1
 /* fftl2_i                        */
 #define    fftl2_i_ADDRESS                  1548
 #define    fftl2_i_OFFSET                     5
 #define    fftl2_i_NBBIT                      1
 #define    fftl2_i_ALONE                      0
 #define    fftl2_i_SIGNED                     0
  #define           fftl2_i_unlocked                           0
  #define           fftl2_i_locked                             1
 /* agcl2_i                        */
 #define    agcl2_i_ADDRESS                  1548
 #define    agcl2_i_OFFSET                     6
 #define    agcl2_i_NBBIT                      1
 #define    agcl2_i_ALONE                      0
 #define    agcl2_i_SIGNED                     0
  #define           agcl2_i_unlocked                           0
  #define           agcl2_i_locked                             1
 /* aafl2_i                        */
 #define    aafl2_i_ADDRESS                  1549
 #define    aafl2_i_OFFSET                     0
 #define    aafl2_i_NBBIT                      1
 #define    aafl2_i_ALONE                      0
 #define    aafl2_i_SIGNED                     0
  #define           aafl2_i_unlocked                           0
  #define           aafl2_i_locked                             1
 /* acil2_i                        */
 #define    acil2_i_ADDRESS                  1549
 #define    acil2_i_OFFSET                     1
 #define    acil2_i_NBBIT                      1
 #define    acil2_i_ALONE                      0
 #define    acil2_i_SIGNED                     0
  #define           acil2_i_unlocked                           0
  #define           acil2_i_locked                             1
 /* correll2_i                     */
 #define    correll2_i_ADDRESS               1549
 #define    correll2_i_OFFSET                  2
 #define    correll2_i_NBBIT                   1
 #define    correll2_i_ALONE                   0
 #define    correll2_i_SIGNED                  0
  #define           correll2_i_unlocked                        0
  #define           correll2_i_locked                          1
 /* psl2_i                         */
 #define    psl2_i_ADDRESS                   1549
 #define    psl2_i_OFFSET                      3
 #define    psl2_i_NBBIT                       1
 #define    psl2_i_ALONE                       0
 #define    psl2_i_SIGNED                      0
  #define           psl2_i_unlocked                            0
  #define           psl2_i_locked                              1
 /* wde2_i                         */
 #define    wde2_i_ADDRESS                   1549
 #define    wde2_i_OFFSET                      4
 #define    wde2_i_NBBIT                       1
 #define    wde2_i_ALONE                       0
 #define    wde2_i_SIGNED                      0
  #define           wde2_i_no_error                            0
  #define           wde2_i_error                               1
 /* trape2_i                       */
 #define    trape2_i_ADDRESS                 1549
 #define    trape2_i_OFFSET                    5
 #define    trape2_i_NBBIT                     1
 #define    trape2_i_ALONE                     0
 #define    trape2_i_SIGNED                    0
  #define           trape2_i_no_error                          0
  #define           trape2_i_error                             1
 /* gp3_p                          */
 #define    gp3_p_ADDRESS                    1552
 #define    gp3_p_OFFSET                       0
 #define    gp3_p_NBBIT                        1
 #define    gp3_p_ALONE                        0
 #define    gp3_p_SIGNED                       0
  #define           gp3_p_non_inverted                         0
  #define           gp3_p_inverted                             1
 /* gp3_t                          */
 #define    gp3_t_ADDRESS                    1552
 #define    gp3_t_OFFSET                       1
 #define    gp3_t_NBBIT                        1
 #define    gp3_t_ALONE                        0
 #define    gp3_t_SIGNED                       0
  #define           gp3_t_cmos                                 0
  #define           gp3_t_open_drain                           1
 /* gp3_en                         */
 #define    gp3_en_ADDRESS                   1552
 #define    gp3_en_OFFSET                      2
 #define    gp3_en_NBBIT                       1
 #define    gp3_en_ALONE                       0
 #define    gp3_en_SIGNED                      0
  #define           gp3_en_disable                             0
  #define           gp3_en_enable                              1
 /* gp3_o                          */
 #define    gp3_o_ADDRESS                    1552
 #define    gp3_o_OFFSET                       3
 #define    gp3_o_NBBIT                        1
 #define    gp3_o_ALONE                        0
 #define    gp3_o_SIGNED                       0
  #define           gp3_o_low                                  0
  #define           gp3_o_high                                 1
 /* gp3_i                          */
 #define    gp3_i_ADDRESS                    1556
 #define    gp3_i_OFFSET                       0
 #define    gp3_i_NBBIT                        1
 #define    gp3_i_ALONE                        1
 #define    gp3_i_SIGNED                       0
  #define           gp3_i_low                                  0
  #define           gp3_i_high                                 1
 /* gp4_p                          */
 #define    gp4_p_ADDRESS                    1569
 #define    gp4_p_OFFSET                       0
 #define    gp4_p_NBBIT                        1
 #define    gp4_p_ALONE                        0
 #define    gp4_p_SIGNED                       0
  #define           gp4_p_non_inverted                         0
  #define           gp4_p_inverted                             1
 /* gp4_t                          */
 #define    gp4_t_ADDRESS                    1569
 #define    gp4_t_OFFSET                       1
 #define    gp4_t_NBBIT                        1
 #define    gp4_t_ALONE                        0
 #define    gp4_t_SIGNED                       0
  #define           gp4_t_cmos                                 0
  #define           gp4_t_open_drain                           1
 /* gp4_en                         */
 #define    gp4_en_ADDRESS                   1569
 #define    gp4_en_OFFSET                      2
 #define    gp4_en_NBBIT                       1
 #define    gp4_en_ALONE                       0
 #define    gp4_en_SIGNED                      0
  #define           gp4_en_disable                             0
  #define           gp4_en_enable                              1
 /* gp4_o                          */
 #define    gp4_o_ADDRESS                    1569
 #define    gp4_o_OFFSET                       3
 #define    gp4_o_NBBIT                        1
 #define    gp4_o_ALONE                        0
 #define    gp4_o_SIGNED                       0
  #define           gp4_o_low                                  0
  #define           gp4_o_high                                 1
 /* gp4_i                          */
 #define    gp4_i_ADDRESS                    1573
 #define    gp4_i_OFFSET                       0
 #define    gp4_i_NBBIT                        1
 #define    gp4_i_ALONE                        1
 #define    gp4_i_SIGNED                       0
  #define           gp4_i_low                                  0
  #define           gp4_i_high                                 1
 /* gp5_p                          */
 #define    gp5_p_ADDRESS                    1586
 #define    gp5_p_OFFSET                       0
 #define    gp5_p_NBBIT                        1
 #define    gp5_p_ALONE                        0
 #define    gp5_p_SIGNED                       0
  #define           gp5_p_non_inverted                         0
  #define           gp5_p_inverted                             1
 /* gp5_t                          */
 #define    gp5_t_ADDRESS                    1586
 #define    gp5_t_OFFSET                       1
 #define    gp5_t_NBBIT                        1
 #define    gp5_t_ALONE                        0
 #define    gp5_t_SIGNED                       0
  #define           gp5_t_cmos                                 0
  #define           gp5_t_open_drain                           1
 /* gp5_en                         */
 #define    gp5_en_ADDRESS                   1586
 #define    gp5_en_OFFSET                      2
 #define    gp5_en_NBBIT                       1
 #define    gp5_en_ALONE                       0
 #define    gp5_en_SIGNED                      0
  #define           gp5_en_disable                             0
  #define           gp5_en_enable                              1
 /* gp5_o                          */
 #define    gp5_o_ADDRESS                    1586
 #define    gp5_o_OFFSET                       3
 #define    gp5_o_NBBIT                        1
 #define    gp5_o_ALONE                        0
 #define    gp5_o_SIGNED                       0
  #define           gp5_o_low                                  0
  #define           gp5_o_high                                 1
 /* gp5_i                          */
 #define    gp5_i_ADDRESS                    1590
 #define    gp5_i_OFFSET                       0
 #define    gp5_i_NBBIT                        1
 #define    gp5_i_ALONE                        1
 #define    gp5_i_SIGNED                       0
  #define           gp5_i_low                                  0
  #define           gp5_i_high                                 1
 /* en_rssi                        */
 #define    en_rssi_ADDRESS                  1601
 #define    en_rssi_OFFSET                     0
 #define    en_rssi_NBBIT                      1
 #define    en_rssi_ALONE                      0
 #define    en_rssi_SIGNED                     0
  #define           en_rssi_off                                0
  #define           en_rssi_on                                 1
 /* start_rssi                     */
 #define    start_rssi_ADDRESS               1601
 #define    start_rssi_OFFSET                  1
 #define    start_rssi_NBBIT                   1
 #define    start_rssi_ALONE                   0
 #define    start_rssi_SIGNED                  0
 /* rssi_update_time               */
 #define    rssi_update_time_ADDRESS         1601
 #define    rssi_update_time_OFFSET            2
 #define    rssi_update_time_NBBIT             5
 #define    rssi_update_time_ALONE             0
 #define    rssi_update_time_SIGNED            0
 /* rssi                           */
 #define    rssi_ADDRESS                     1602
 #define    rssi_OFFSET                        0
 #define    rssi_NBBIT                         8
 #define    rssi_ALONE                         1
 #define    rssi_SIGNED                        0
 /* rssi_pad_ctrl                  */
 #define    rssi_pad_ctrl_ADDRESS            1606
 #define    rssi_pad_ctrl_OFFSET               0
 #define    rssi_pad_ctrl_NBBIT                2
 #define    rssi_pad_ctrl_ALONE                1
 #define    rssi_pad_ctrl_SIGNED               0
  #define           rssi_pad_ctrl_adc_in                       0
  #define           rssi_pad_ctrl_xtal_out                     1
  #define           rssi_pad_ctrl_diag                         2
 /* addr_tuner                     */
 #define    addr_tuner_ADDRESS               1616
 #define    addr_tuner_OFFSET                  0
 #define    addr_tuner_NBBIT                   7
 #define    addr_tuner_ALONE                   1
 #define    addr_tuner_SIGNED                  0
 /* addr_offset                    */
 #define    addr_offset_ADDRESS              1620
 #define    addr_offset_OFFSET                 0
 #define    addr_offset_NBBIT                 16
 #define    addr_offset_ALONE                  1
 #define    addr_offset_SIGNED                 0
 /* addr_offset_length             */
 #define    addr_offset_length_ADDRESS       1624
 #define    addr_offset_length_OFFSET          0
 #define    addr_offset_length_NBBIT           1
 #define    addr_offset_length_ALONE           1
 #define    addr_offset_length_SIGNED          0
  #define           addr_offset_length_16_bits                 1
  #define           addr_offset_length_8_bits                  0
 /* use_read_addr_offset           */
 #define    use_read_addr_offset_ADDRESS     1625
 #define    use_read_addr_offset_OFFSET        0
 #define    use_read_addr_offset_NBBIT         1
 #define    use_read_addr_offset_ALONE         0
 #define    use_read_addr_offset_SIGNED        0
  #define           use_read_addr_offset_yes                   1
  #define           use_read_addr_offset_no                    0
 /* use_write_addr_offset          */
 #define    use_write_addr_offset_ADDRESS    1625
 #define    use_write_addr_offset_OFFSET       1
 #define    use_write_addr_offset_NBBIT        1
 #define    use_write_addr_offset_ALONE        0
 #define    use_write_addr_offset_SIGNED       0
  #define           use_write_addr_offset_yes                  1
  #define           use_write_addr_offset_no                   0
 /* ack_last_read_byte             */
 #define    ack_last_read_byte_ADDRESS       1626
 #define    ack_last_read_byte_OFFSET          0
 #define    ack_last_read_byte_NBBIT           1
 #define    ack_last_read_byte_ALONE           1
 #define    ack_last_read_byte_SIGNED          0
  #define           ack_last_read_byte_yes                     1
  #define           ack_last_read_byte_no                      0
 /* tuner_write_ctrl               */
 #define    tuner_write_ctrl_ADDRESS         1628
 #define    tuner_write_ctrl_OFFSET            0
 #define    tuner_write_ctrl_NBBIT            16
 #define    tuner_write_ctrl_ALONE             1
 #define    tuner_write_ctrl_SIGNED            0
 /* tuner_read_ctrl                */
 #define    tuner_read_ctrl_ADDRESS          1632
 #define    tuner_read_ctrl_OFFSET             0
 #define    tuner_read_ctrl_NBBIT             16
 #define    tuner_read_ctrl_ALONE              1
 #define    tuner_read_ctrl_SIGNED             0
 /* tuner_write_done               */
 #define    tuner_write_done_ADDRESS         1636
 #define    tuner_write_done_OFFSET            0
 #define    tuner_write_done_NBBIT             1
 #define    tuner_write_done_ALONE             0
 #define    tuner_write_done_SIGNED            0
  #define           tuner_write_done_yes                       1
  #define           tuner_write_done_no                        0
 /* tuner_read_done                */
 #define    tuner_read_done_ADDRESS          1636
 #define    tuner_read_done_OFFSET             1
 #define    tuner_read_done_NBBIT              1
 #define    tuner_read_done_ALONE              0
 #define    tuner_read_done_SIGNED             0
  #define           tuner_read_done_yes                        1
  #define           tuner_read_done_no                         0
 /* ack_check                      */
 #define    ack_check_ADDRESS                1636
 #define    ack_check_OFFSET                   2
 #define    ack_check_NBBIT                    1
 #define    ack_check_ALONE                    0
 #define    ack_check_SIGNED                   0
  #define           ack_check_error                            1
  #define           ack_check_no_error                         0
 /* scl_frequency                  */
 #define    scl_frequency_ADDRESS            1640
 #define    scl_frequency_OFFSET               0
 #define    scl_frequency_NBBIT               10
 #define    scl_frequency_ALONE                1
 #define    scl_frequency_SIGNED               0
 /* tuner_write_reg0               */
 #define    tuner_write_reg0_ADDRESS         1644
 #define    tuner_write_reg0_OFFSET            0
 #define    tuner_write_reg0_NBBIT             8
 #define    tuner_write_reg0_ALONE             1
 #define    tuner_write_reg0_SIGNED            0
 /* tuner_write_reg1               */
 #define    tuner_write_reg1_ADDRESS         1645
 #define    tuner_write_reg1_OFFSET            0
 #define    tuner_write_reg1_NBBIT             8
 #define    tuner_write_reg1_ALONE             1
 #define    tuner_write_reg1_SIGNED            0
 /* tuner_write_reg2               */
 #define    tuner_write_reg2_ADDRESS         1646
 #define    tuner_write_reg2_OFFSET            0
 #define    tuner_write_reg2_NBBIT             8
 #define    tuner_write_reg2_ALONE             1
 #define    tuner_write_reg2_SIGNED            0
 /* tuner_write_reg3               */
 #define    tuner_write_reg3_ADDRESS         1647
 #define    tuner_write_reg3_OFFSET            0
 #define    tuner_write_reg3_NBBIT             8
 #define    tuner_write_reg3_ALONE             1
 #define    tuner_write_reg3_SIGNED            0
 /* tuner_write_reg4               */
 #define    tuner_write_reg4_ADDRESS         1648
 #define    tuner_write_reg4_OFFSET            0
 #define    tuner_write_reg4_NBBIT             8
 #define    tuner_write_reg4_ALONE             1
 #define    tuner_write_reg4_SIGNED            0
 /* tuner_write_reg5               */
 #define    tuner_write_reg5_ADDRESS         1649
 #define    tuner_write_reg5_OFFSET            0
 #define    tuner_write_reg5_NBBIT             8
 #define    tuner_write_reg5_ALONE             1
 #define    tuner_write_reg5_SIGNED            0
 /* tuner_write_reg6               */
 #define    tuner_write_reg6_ADDRESS         1650
 #define    tuner_write_reg6_OFFSET            0
 #define    tuner_write_reg6_NBBIT             8
 #define    tuner_write_reg6_ALONE             1
 #define    tuner_write_reg6_SIGNED            0
 /* tuner_write_reg7               */
 #define    tuner_write_reg7_ADDRESS         1651
 #define    tuner_write_reg7_OFFSET            0
 #define    tuner_write_reg7_NBBIT             8
 #define    tuner_write_reg7_ALONE             1
 #define    tuner_write_reg7_SIGNED            0
 /* tuner_write_reg8               */
 #define    tuner_write_reg8_ADDRESS         1652
 #define    tuner_write_reg8_OFFSET            0
 #define    tuner_write_reg8_NBBIT             8
 #define    tuner_write_reg8_ALONE             1
 #define    tuner_write_reg8_SIGNED            0
 /* tuner_write_reg9               */
 #define    tuner_write_reg9_ADDRESS         1653
 #define    tuner_write_reg9_OFFSET            0
 #define    tuner_write_reg9_NBBIT             8
 #define    tuner_write_reg9_ALONE             1
 #define    tuner_write_reg9_SIGNED            0
 /* tuner_write_reg10              */
 #define    tuner_write_reg10_ADDRESS        1654
 #define    tuner_write_reg10_OFFSET           0
 #define    tuner_write_reg10_NBBIT            8
 #define    tuner_write_reg10_ALONE            1
 #define    tuner_write_reg10_SIGNED           0
 /* tuner_write_reg11              */
 #define    tuner_write_reg11_ADDRESS        1655
 #define    tuner_write_reg11_OFFSET           0
 #define    tuner_write_reg11_NBBIT            8
 #define    tuner_write_reg11_ALONE            1
 #define    tuner_write_reg11_SIGNED           0
 /* tuner_write_reg12              */
 #define    tuner_write_reg12_ADDRESS        1656
 #define    tuner_write_reg12_OFFSET           0
 #define    tuner_write_reg12_NBBIT            8
 #define    tuner_write_reg12_ALONE            1
 #define    tuner_write_reg12_SIGNED           0
 /* tuner_write_reg13              */
 #define    tuner_write_reg13_ADDRESS        1657
 #define    tuner_write_reg13_OFFSET           0
 #define    tuner_write_reg13_NBBIT            8
 #define    tuner_write_reg13_ALONE            1
 #define    tuner_write_reg13_SIGNED           0
 /* tuner_write_reg14              */
 #define    tuner_write_reg14_ADDRESS        1658
 #define    tuner_write_reg14_OFFSET           0
 #define    tuner_write_reg14_NBBIT            8
 #define    tuner_write_reg14_ALONE            1
 #define    tuner_write_reg14_SIGNED           0
 /* tuner_write_reg15              */
 #define    tuner_write_reg15_ADDRESS        1659
 #define    tuner_write_reg15_OFFSET           0
 #define    tuner_write_reg15_NBBIT            8
 #define    tuner_write_reg15_ALONE            1
 #define    tuner_write_reg15_SIGNED           0
 /* tuner_read_reg0                */
 #define    tuner_read_reg0_ADDRESS          1660
 #define    tuner_read_reg0_OFFSET             0
 #define    tuner_read_reg0_NBBIT              8
 #define    tuner_read_reg0_ALONE              1
 #define    tuner_read_reg0_SIGNED             0
 /* tuner_read_reg1                */
 #define    tuner_read_reg1_ADDRESS          1661
 #define    tuner_read_reg1_OFFSET             0
 #define    tuner_read_reg1_NBBIT              8
 #define    tuner_read_reg1_ALONE              1
 #define    tuner_read_reg1_SIGNED             0
 /* tuner_read_reg2                */
 #define    tuner_read_reg2_ADDRESS          1662
 #define    tuner_read_reg2_OFFSET             0
 #define    tuner_read_reg2_NBBIT              8
 #define    tuner_read_reg2_ALONE              1
 #define    tuner_read_reg2_SIGNED             0
 /* tuner_read_reg3                */
 #define    tuner_read_reg3_ADDRESS          1663
 #define    tuner_read_reg3_OFFSET             0
 #define    tuner_read_reg3_NBBIT              8
 #define    tuner_read_reg3_ALONE              1
 #define    tuner_read_reg3_SIGNED             0
 /* tuner_read_reg4                */
 #define    tuner_read_reg4_ADDRESS          1664
 #define    tuner_read_reg4_OFFSET             0
 #define    tuner_read_reg4_NBBIT              8
 #define    tuner_read_reg4_ALONE              1
 #define    tuner_read_reg4_SIGNED             0
 /* tuner_read_reg5                */
 #define    tuner_read_reg5_ADDRESS          1665
 #define    tuner_read_reg5_OFFSET             0
 #define    tuner_read_reg5_NBBIT              8
 #define    tuner_read_reg5_ALONE              1
 #define    tuner_read_reg5_SIGNED             0
 /* tuner_read_reg6                */
 #define    tuner_read_reg6_ADDRESS          1666
 #define    tuner_read_reg6_OFFSET             0
 #define    tuner_read_reg6_NBBIT              8
 #define    tuner_read_reg6_ALONE              1
 #define    tuner_read_reg6_SIGNED             0
 /* tuner_read_reg7                */
 #define    tuner_read_reg7_ADDRESS          1667
 #define    tuner_read_reg7_OFFSET             0
 #define    tuner_read_reg7_NBBIT              8
 #define    tuner_read_reg7_ALONE              1
 #define    tuner_read_reg7_SIGNED             0
 /* tuner_read_reg8                */
 #define    tuner_read_reg8_ADDRESS          1668
 #define    tuner_read_reg8_OFFSET             0
 #define    tuner_read_reg8_NBBIT              8
 #define    tuner_read_reg8_ALONE              1
 #define    tuner_read_reg8_SIGNED             0
 /* tuner_read_reg9                */
 #define    tuner_read_reg9_ADDRESS          1669
 #define    tuner_read_reg9_OFFSET             0
 #define    tuner_read_reg9_NBBIT              8
 #define    tuner_read_reg9_ALONE              1
 #define    tuner_read_reg9_SIGNED             0
 /* tuner_read_reg10               */
 #define    tuner_read_reg10_ADDRESS         1670
 #define    tuner_read_reg10_OFFSET            0
 #define    tuner_read_reg10_NBBIT             8
 #define    tuner_read_reg10_ALONE             1
 #define    tuner_read_reg10_SIGNED            0
 /* tuner_read_reg11               */
 #define    tuner_read_reg11_ADDRESS         1671
 #define    tuner_read_reg11_OFFSET            0
 #define    tuner_read_reg11_NBBIT             8
 #define    tuner_read_reg11_ALONE             1
 #define    tuner_read_reg11_SIGNED            0
 /* tuner_read_reg12               */
 #define    tuner_read_reg12_ADDRESS         1672
 #define    tuner_read_reg12_OFFSET            0
 #define    tuner_read_reg12_NBBIT             8
 #define    tuner_read_reg12_ALONE             1
 #define    tuner_read_reg12_SIGNED            0
 /* tuner_read_reg13               */
 #define    tuner_read_reg13_ADDRESS         1673
 #define    tuner_read_reg13_OFFSET            0
 #define    tuner_read_reg13_NBBIT             8
 #define    tuner_read_reg13_ALONE             1
 #define    tuner_read_reg13_SIGNED            0
 /* tuner_read_reg14               */
 #define    tuner_read_reg14_ADDRESS         1674
 #define    tuner_read_reg14_OFFSET            0
 #define    tuner_read_reg14_NBBIT             8
 #define    tuner_read_reg14_ALONE             1
 #define    tuner_read_reg14_SIGNED            0
 /* tuner_read_reg15               */
 #define    tuner_read_reg15_ADDRESS         1675
 #define    tuner_read_reg15_OFFSET            0
 #define    tuner_read_reg15_NBBIT             8
 #define    tuner_read_reg15_ALONE             1
 #define    tuner_read_reg15_SIGNED            0
 /* div_by_decided                 */
 #define    div_by_decided_ADDRESS           1680
 #define    div_by_decided_OFFSET              0
 #define    div_by_decided_NBBIT               1
 #define    div_by_decided_ALONE               1
 #define    div_by_decided_SIGNED              0
  #define           div_by_decided_disable                     0
  #define           div_by_decided_enable                      1
 /* muldiv                         */
 #define    muldiv_ADDRESS                   1684
 #define    muldiv_OFFSET                      0
 #define    muldiv_NBBIT                       1
 #define    muldiv_ALONE                       1
 #define    muldiv_SIGNED                      0
  #define           muldiv_mul                                 0
  #define           muldiv_div                                 1
 /* conjugate                      */
 #define    conjugate_ADDRESS                1688
 #define    conjugate_OFFSET                   0
 #define    conjugate_NBBIT                    1
 #define    conjugate_ALONE                    1
 #define    conjugate_SIGNED                   0
  #define           conjugate_disable                          0
  #define           conjugate_enable                           1
 /* proc_gain                      */
 #define    proc_gain_ADDRESS                1692
 #define    proc_gain_OFFSET                   0
 #define    proc_gain_NBBIT                    4
 #define    proc_gain_ALONE                    1
 #define    proc_gain_SIGNED                   1
 /* oper_a_in                      */
 #define    oper_a_in_ADDRESS                1696
 #define    oper_a_in_OFFSET                   0
 #define    oper_a_in_NBBIT                    4
 #define    oper_a_in_ALONE                    1
 #define    oper_a_in_SIGNED                   0
  #define           oper_a_in_dma1                             0
  #define           oper_a_in_dma2                             1
  #define           oper_a_in_dma3                             2
  #define           oper_a_in_dma4                             3
  #define           oper_a_in_pk                               4
  #define           oper_a_in_pk_4                             5
  #define           oper_a_in_gp                               6
  #define           oper_a_in_gp_decided                       7
  #define           oper_a_in_idma1_qdma2                      8
  #define           oper_a_in_idma1_qdma3                      9
  #define           oper_a_in_idma1_qdma4                     10
  #define           oper_a_in_idma2_qdma3                     11
  #define           oper_a_in_idma2_qdma4                     12
  #define           oper_a_in_idma3_qdma4                     13
 /* oper_b_in                      */
 #define    oper_b_in_ADDRESS                1700
 #define    oper_b_in_OFFSET                   0
 #define    oper_b_in_NBBIT                    4
 #define    oper_b_in_ALONE                    1
 #define    oper_b_in_SIGNED                   0
  #define           oper_b_in_dma1                             0
  #define           oper_b_in_dma2                             1
  #define           oper_b_in_dma3                             2
  #define           oper_b_in_dma4                             3
  #define           oper_b_in_pk                               4
  #define           oper_b_in_pk_4                             5
  #define           oper_b_in_gp                               6
  #define           oper_b_in_gp_decided                       7
  #define           oper_b_in_idma1_qdma2                      8
  #define           oper_b_in_idma1_qdma3                      9
  #define           oper_b_in_idma1_qdma4                     10
  #define           oper_b_in_idma2_qdma3                     11
  #define           oper_b_in_idma2_qdma4                     12
  #define           oper_b_in_idma3_qdma4                     13
 /* sel_output1                    */
 #define    sel_output1_ADDRESS              1704
 #define    sel_output1_OFFSET                 0
 #define    sel_output1_NBBIT                  3
 #define    sel_output1_ALONE                  1
 #define    sel_output1_SIGNED                 0
  #define           sel_output1_operator                       0
  #define           sel_output1_pk                             1
  #define           sel_output1_pk_4                           2
  #define           sel_output1_gp                             3
  #define           sel_output1_gp_decided                     4
 /* sel_output2                    */
 #define    sel_output2_ADDRESS              1708
 #define    sel_output2_OFFSET                 0
 #define    sel_output2_NBBIT                  3
 #define    sel_output2_ALONE                  1
 #define    sel_output2_SIGNED                 0
  #define           sel_output2_operator                       0
  #define           sel_output2_pk                             1
  #define           sel_output2_pk_4                           2
  #define           sel_output2_gp                             3
  #define           sel_output2_gp_decided                     4
 /* sel_output3                    */
 #define    sel_output3_ADDRESS              1712
 #define    sel_output3_OFFSET                 0
 #define    sel_output3_NBBIT                  3
 #define    sel_output3_ALONE                  1
 #define    sel_output3_SIGNED                 0
  #define           sel_output3_operator                       0
  #define           sel_output3_pk                             1
  #define           sel_output3_pk_4                           2
  #define           sel_output3_gp                             3
  #define           sel_output3_gp_decided                     4
 /* sel_output4                    */
 #define    sel_output4_ADDRESS              1716
 #define    sel_output4_OFFSET                 0
 #define    sel_output4_NBBIT                  3
 #define    sel_output4_ALONE                  1
 #define    sel_output4_SIGNED                 0
  #define           sel_output4_operator                       0
  #define           sel_output4_pk                             1
  #define           sel_output4_pk_4                           2
  #define           sel_output4_gp                             3
  #define           sel_output4_gp_decided                     4
 /* car_output1                    */
 #define    car_output1_ADDRESS              1720
 #define    car_output1_OFFSET                 0
 #define    car_output1_NBBIT                  4
 #define    car_output1_ALONE                  1
 #define    car_output1_SIGNED                 0
  #define           car_output1_cont                           1
  #define           car_output1_scat                           2
  #define           car_output1_tps                            4
  #define           car_output1_datas                          8
  #define           car_output1_all                           15
 /* car_output2                    */
 #define    car_output2_ADDRESS              1724
 #define    car_output2_OFFSET                 0
 #define    car_output2_NBBIT                  4
 #define    car_output2_ALONE                  1
 #define    car_output2_SIGNED                 0
  #define           car_output2_cont                           1
  #define           car_output2_scat                           2
  #define           car_output2_tps                            4
  #define           car_output2_datas                          8
  #define           car_output2_all                           15
 /* car_output3                    */
 #define    car_output3_ADDRESS              1728
 #define    car_output3_OFFSET                 0
 #define    car_output3_NBBIT                  4
 #define    car_output3_ALONE                  1
 #define    car_output3_SIGNED                 0
  #define           car_output3_cont                           1
  #define           car_output3_scat                           2
  #define           car_output3_tps                            4
  #define           car_output3_datas                          8
  #define           car_output3_all                           15
 /* car_output4                    */
 #define    car_output4_ADDRESS              1732
 #define    car_output4_OFFSET                 0
 #define    car_output4_NBBIT                  4
 #define    car_output4_ALONE                  1
 #define    car_output4_SIGNED                 0
  #define           car_output4_cont                           1
  #define           car_output4_scat                           2
  #define           car_output4_tps                            4
  #define           car_output4_datas                          8
  #define           car_output4_all                           15
 /* sel_format1                    */
 #define    sel_format1_ADDRESS              1736
 #define    sel_format1_OFFSET                 0
 #define    sel_format1_NBBIT                  2
 #define    sel_format1_ALONE                  1
 #define    sel_format1_SIGNED                 0
  #define           sel_format1_iq                             0
  #define           sel_format1_i                              1
  #define           sel_format1_q                              2
 /* sel_format2                    */
 #define    sel_format2_ADDRESS              1740
 #define    sel_format2_OFFSET                 0
 #define    sel_format2_NBBIT                  2
 #define    sel_format2_ALONE                  1
 #define    sel_format2_SIGNED                 0
  #define           sel_format2_iq                             0
  #define           sel_format2_i                              1
  #define           sel_format2_q                              2
 /* sel_format3                    */
 #define    sel_format3_ADDRESS              1744
 #define    sel_format3_OFFSET                 0
 #define    sel_format3_NBBIT                  2
 #define    sel_format3_ALONE                  1
 #define    sel_format3_SIGNED                 0
  #define           sel_format3_iq                             0
  #define           sel_format3_i                              1
  #define           sel_format3_q                              2
 /* sel_format4                    */
 #define    sel_format4_ADDRESS              1748
 #define    sel_format4_OFFSET                 0
 #define    sel_format4_NBBIT                  2
 #define    sel_format4_ALONE                  1
 #define    sel_format4_SIGNED                 0
  #define           sel_format4_iq                             0
  #define           sel_format4_i                              1
  #define           sel_format4_q                              2
 /* sel_ignor_first1               */
 #define    sel_ignor_first1_ADDRESS         1752
 #define    sel_ignor_first1_OFFSET            0
 #define    sel_ignor_first1_NBBIT            13
 #define    sel_ignor_first1_ALONE             1
 #define    sel_ignor_first1_SIGNED            0
 /* sel_ignor_first2               */
 #define    sel_ignor_first2_ADDRESS         1756
 #define    sel_ignor_first2_OFFSET            0
 #define    sel_ignor_first2_NBBIT            13
 #define    sel_ignor_first2_ALONE             1
 #define    sel_ignor_first2_SIGNED            0
 /* sel_ignor_first3               */
 #define    sel_ignor_first3_ADDRESS         1760
 #define    sel_ignor_first3_OFFSET            0
 #define    sel_ignor_first3_NBBIT            13
 #define    sel_ignor_first3_ALONE             1
 #define    sel_ignor_first3_SIGNED            0
 /* sel_ignor_first4               */
 #define    sel_ignor_first4_ADDRESS         1764
 #define    sel_ignor_first4_OFFSET            0
 #define    sel_ignor_first4_NBBIT            13
 #define    sel_ignor_first4_ALONE             1
 #define    sel_ignor_first4_SIGNED            0
 /* delay_oper_a                   */
 #define    delay_oper_a_ADDRESS             1768
 #define    delay_oper_a_OFFSET                0
 #define    delay_oper_a_NBBIT                 1
 #define    delay_oper_a_ALONE                 1
 #define    delay_oper_a_SIGNED                0
  #define           delay_oper_a_off                           0
  #define           delay_oper_a_on                            1
 /* inf_fe_bypass                  */
 #define    inf_fe_bypass_ADDRESS            1776
 #define    inf_fe_bypass_OFFSET               0
 #define    inf_fe_bypass_NBBIT                1
 #define    inf_fe_bypass_ALONE                0
 #define    inf_fe_bypass_SIGNED               0
  #define           inf_fe_bypass_off                          0
  #define           inf_fe_bypass_on                           1
 /* inf_fe_mode                    */
 #define    inf_fe_mode_ADDRESS              1776
 #define    inf_fe_mode_OFFSET                 1
 #define    inf_fe_mode_NBBIT                  2
 #define    inf_fe_mode_ALONE                  0
 #define    inf_fe_mode_SIGNED                 0
  #define           inf_fe_mode_saturate                       0
  #define           inf_fe_mode_blanking                       1
  #define           inf_fe_mode_sat_and_blanking               2
  #define           inf_fe_mode_no_sat_and_blanking            3
 /* inf_fe_sample_thd              */
 #define    inf_fe_sample_thd_ADDRESS        1777
 #define    inf_fe_sample_thd_OFFSET           0
 #define    inf_fe_sample_thd_NBBIT            5
 #define    inf_fe_sample_thd_ALONE            1
 #define    inf_fe_sample_thd_SIGNED           0
 /* inf_fe_burst_thd               */
 #define    inf_fe_burst_thd_ADDRESS         1778
 #define    inf_fe_burst_thd_OFFSET            0
 #define    inf_fe_burst_thd_NBBIT             5
 #define    inf_fe_burst_thd_ALONE             1
 #define    inf_fe_burst_thd_SIGNED            0
 /* inf_fe_sat_thd                 */
 #define    inf_fe_sat_thd_ADDRESS           1780
 #define    inf_fe_sat_thd_OFFSET              0
 #define    inf_fe_sat_thd_NBBIT              10
 #define    inf_fe_sat_thd_ALONE               1
 #define    inf_fe_sat_thd_SIGNED              0
 /* inf_fe_cnt_del                 */
 #define    inf_fe_cnt_del_ADDRESS           1782
 #define    inf_fe_cnt_del_OFFSET              0
 #define    inf_fe_cnt_del_NBBIT              14
 #define    inf_fe_cnt_del_ALONE               1
 #define    inf_fe_cnt_del_SIGNED              0
 /* inf_bypass                     */
 #define    inf_bypass_ADDRESS               1786
 #define    inf_bypass_OFFSET                  0
 #define    inf_bypass_NBBIT                   1
 #define    inf_bypass_ALONE                   0
 #define    inf_bypass_SIGNED                  0
  #define           inf_bypass_off                             0
  #define           inf_bypass_on                              1
 /* inf_mode                       */
 #define    inf_mode_ADDRESS                 1786
 #define    inf_mode_OFFSET                    1
 #define    inf_mode_NBBIT                     2
 #define    inf_mode_ALONE                     0
 #define    inf_mode_SIGNED                    0
  #define           inf_mode_saturate                          0
  #define           inf_mode_blanking                          1
  #define           inf_mode_sat_and_blanking                  2
  #define           inf_mode_no_sat_and_blanking               3
 /* inf_switch                     */
 #define    inf_switch_ADDRESS               1786
 #define    inf_switch_OFFSET                  3
 #define    inf_switch_NBBIT                   1
 #define    inf_switch_ALONE                   0
 #define    inf_switch_SIGNED                  0
  #define           inf_switch_inf_after_fir1                  0
  #define           inf_switch_inf_after_fir2                  1
 /* inf_burst_del_thd1             */
 #define    inf_burst_del_thd1_ADDRESS       1787
 #define    inf_burst_del_thd1_OFFSET          0
 #define    inf_burst_del_thd1_NBBIT           6
 #define    inf_burst_del_thd1_ALONE           1
 #define    inf_burst_del_thd1_SIGNED          0
 /* inf_sample_del_thd1            */
 #define    inf_sample_del_thd1_ADDRESS      1792
 #define    inf_sample_del_thd1_OFFSET         0
 #define    inf_sample_del_thd1_NBBIT          6
 #define    inf_sample_del_thd1_ALONE          1
 #define    inf_sample_del_thd1_SIGNED         0
 /* inf_sat_thd1                   */
 #define    inf_sat_thd1_ADDRESS             1796
 #define    inf_sat_thd1_OFFSET                0
 #define    inf_sat_thd1_NBBIT                 9
 #define    inf_sat_thd1_ALONE                 1
 #define    inf_sat_thd1_SIGNED                0
 /* inf_cnt_del                    */
 #define    inf_cnt_del_ADDRESS              1798
 #define    inf_cnt_del_OFFSET                 0
 #define    inf_cnt_del_NBBIT                 14
 #define    inf_cnt_del_ALONE                  1
 #define    inf_cnt_del_SIGNED                 0
 /* gain_fft                       */
 #define    gain_fft_ADDRESS                 1808
 #define    gain_fft_OFFSET                    0
 #define    gain_fft_NBBIT                     4
 #define    gain_fft_ALONE                     1
 #define    gain_fft_SIGNED                    0
 /* use_sqrt_2                     */
 #define    use_sqrt_2_ADDRESS               1809
 #define    use_sqrt_2_OFFSET                  0
 #define    use_sqrt_2_NBBIT                   1
 #define    use_sqrt_2_ALONE                   1
 #define    use_sqrt_2_SIGNED                  0
 /* hold_shift                     */
 #define    hold_shift_ADDRESS               1812
 #define    hold_shift_OFFSET                  0
 #define    hold_shift_NBBIT                   1
 #define    hold_shift_ALONE                   0
 #define    hold_shift_SIGNED                  0
  #define           hold_shift_running_shift_ratio             0
  #define           hold_shift_hold_shift_ratio                1
 /* shift_load                     */
 #define    shift_load_ADDRESS               1812
 #define    shift_load_OFFSET                  1
 #define    shift_load_NBBIT                   1
 #define    shift_load_ALONE                   0
 #define    shift_load_SIGNED                  0
  #define           shift_load_running                         0
  #define           shift_load_load_shift_in_value             1
 /* use_adjustment                 */
 #define    use_adjustment_ADDRESS           1813
 #define    use_adjustment_OFFSET              0
 #define    use_adjustment_NBBIT               1
 #define    use_adjustment_ALONE               1
 #define    use_adjustment_SIGNED              0
  #define           use_adjustment_off                         0
  #define           use_adjustment_on                          1
 /* shift_speed                    */
 #define    shift_speed_ADDRESS              1816
 #define    shift_speed_OFFSET                 0
 #define    shift_speed_NBBIT                  3
 #define    shift_speed_ALONE                  1
 #define    shift_speed_SIGNED                 0
 /* shift_sgn_in                   */
 #define    shift_sgn_in_ADDRESS             1820
 #define    shift_sgn_in_OFFSET                0
 #define    shift_sgn_in_NBBIT                14
 #define    shift_sgn_in_ALONE                 1
 #define    shift_sgn_in_SIGNED                1
 /* shift_sgn_out                  */
 #define    shift_sgn_out_ADDRESS            1824
 #define    shift_sgn_out_OFFSET               0
 #define    shift_sgn_out_NBBIT               14
 #define    shift_sgn_out_ALONE                1
 #define    shift_sgn_out_SIGNED               1
 /* gain_linear                    */
 #define    gain_linear_ADDRESS              1828
 #define    gain_linear_OFFSET                 0
 #define    gain_linear_NBBIT                 10
 #define    gain_linear_ALONE                  1
 #define    gain_linear_SIGNED                 0
 /* deferred_iir                   */
 #define    deferred_iir_ADDRESS             1843
 #define    deferred_iir_OFFSET                0
 #define    deferred_iir_NBBIT                 5
 #define    deferred_iir_ALONE                 1
 #define    deferred_iir_SIGNED                0
 /* time_filter                    */
 #define    time_filter_ADDRESS              1844
 #define    time_filter_OFFSET                 0
 #define    time_filter_NBBIT                  3
 #define    time_filter_ALONE                  1
 #define    time_filter_SIGNED                 0
  #define           time_filter_iir                            0
  #define           time_filter_pred                           1
  #define           time_filter_2pilots                        2
  #define           time_filter_4pilots                        3
  #define           time_filter_8pilots                        4
 /* bw_iir                         */
 #define    bw_iir_ADDRESS                   1845
 #define    bw_iir_OFFSET                      0
 #define    bw_iir_NBBIT                       2
 #define    bw_iir_ALONE                       0
 #define    bw_iir_SIGNED                      0
  #define           bw_iir_1_8                                 1
  #define           bw_iir_1_16                                2
  #define           bw_iir_1_32                                3
  #define           bw_iir_1_4                                 0
 /* pred_filter                    */
 #define    pred_filter_ADDRESS              1845
 #define    pred_filter_OFFSET                 2
 #define    pred_filter_NBBIT                  1
 #define    pred_filter_ALONE                  0
 #define    pred_filter_SIGNED                 0
  #define           pred_filter_filter1                        0
  #define           pred_filter_filter2                        1
 /* freq_filter                    */
 #define    freq_filter_ADDRESS              1846
 #define    freq_filter_OFFSET                 0
 #define    freq_filter_NBBIT                  3
 #define    freq_filter_ALONE                  1
 #define    freq_filter_SIGNED                 0
  #define           freq_filter_1_32                           0
  #define           freq_filter_1_16                           1
  #define           freq_filter_1_8                            2
  #define           freq_filter_1_4                            3
  #define           freq_filter_7_24                           4
 /* cci_erasing                    */
 #define    cci_erasing_ADDRESS              1856
 #define    cci_erasing_OFFSET                 1
 #define    cci_erasing_NBBIT                  1
 #define    cci_erasing_ALONE                  1
 #define    cci_erasing_SIGNED                 0
  #define           cci_erasing_off                            0
  #define           cci_erasing_on                             1
 /* cci_erasing_level              */
 #define    cci_erasing_level_ADDRESS        1857
 #define    cci_erasing_level_OFFSET           0
 #define    cci_erasing_level_NBBIT            4
 #define    cci_erasing_level_ALONE            1
 #define    cci_erasing_level_SIGNED           0
 /* cci_erasing_cnt                */
 #define    cci_erasing_cnt_ADDRESS          1858
 #define    cci_erasing_cnt_OFFSET             0
 #define    cci_erasing_cnt_NBBIT              8
 #define    cci_erasing_cnt_ALONE              1
 #define    cci_erasing_cnt_SIGNED             0
 /* start_cluster_cfd1             */
 #define    start_cluster_cfd1_ADDRESS       1860
 #define    start_cluster_cfd1_OFFSET          0
 #define    start_cluster_cfd1_NBBIT          16
 #define    start_cluster_cfd1_ALONE           1
 #define    start_cluster_cfd1_SIGNED          0
 /* end_cluster_cfd1               */
 #define    end_cluster_cfd1_ADDRESS         1862
 #define    end_cluster_cfd1_OFFSET            0
 #define    end_cluster_cfd1_NBBIT            16
 #define    end_cluster_cfd1_ALONE             1
 #define    end_cluster_cfd1_SIGNED            0
 /* noise_filter                   */
 #define    noise_filter_ADDRESS             1864
 #define    noise_filter_OFFSET                0
 #define    noise_filter_NBBIT                 2
 #define    noise_filter_ALONE                 1
 #define    noise_filter_SIGNED                0
  #define           noise_filter_1_8                           0
  #define           noise_filter_1_64                          1
  #define           noise_filter_1_128                         2
  #define           noise_filter_1_256                         3
 /* noise_power_mode               */
 #define    noise_power_mode_ADDRESS         1865
 #define    noise_power_mode_OFFSET            0
 #define    noise_power_mode_NBBIT             2
 #define    noise_power_mode_ALONE             1
 #define    noise_power_mode_SIGNED            0
  #define           noise_power_mode_pilots                    0
  #define           noise_power_mode_constel                   1
  #define           noise_power_mode_constel_full              2
 /* csi_mode                       */
 #define    csi_mode_ADDRESS                 1866
 #define    csi_mode_OFFSET                    0
 #define    csi_mode_NBBIT                     1
 #define    csi_mode_ALONE                     0
 #define    csi_mode_SIGNED                    0
  #define           csi_mode_fading                            0
  #define           csi_mode_cci                               1
 /* mean_power_mode                */
 #define    mean_power_mode_ADDRESS          1866
 #define    mean_power_mode_OFFSET             2
 #define    mean_power_mode_NBBIT              1
 #define    mean_power_mode_ALONE              0
 #define    mean_power_mode_SIGNED             0
  #define           mean_power_mode_pre_filter                 0
  #define           mean_power_mode_post_filter                1
 /* cluster_size                   */
 #define    cluster_size_ADDRESS             1867
 #define    cluster_size_OFFSET                0
 #define    cluster_size_NBBIT                 4
 #define    cluster_size_ALONE                 1
 #define    cluster_size_SIGNED                0
 /* start_cluster1                 */
 #define    start_cluster1_ADDRESS           1868
 #define    start_cluster1_OFFSET              0
 #define    start_cluster1_NBBIT              16
 #define    start_cluster1_ALONE               1
 #define    start_cluster1_SIGNED              0
 /* end_cluster1                   */
 #define    end_cluster1_ADDRESS             1870
 #define    end_cluster1_OFFSET                0
 #define    end_cluster1_NBBIT                16
 #define    end_cluster1_ALONE                 1
 #define    end_cluster1_SIGNED                0
 /* start_cluster2                 */
 #define    start_cluster2_ADDRESS           1872
 #define    start_cluster2_OFFSET              0
 #define    start_cluster2_NBBIT              16
 #define    start_cluster2_ALONE               1
 #define    start_cluster2_SIGNED              0
 /* end_cluster2                   */
 #define    end_cluster2_ADDRESS             1874
 #define    end_cluster2_OFFSET                0
 #define    end_cluster2_NBBIT                16
 #define    end_cluster2_ALONE                 1
 #define    end_cluster2_SIGNED                0
 /* start_cluster_cfd0             */
 #define    start_cluster_cfd0_ADDRESS       1876
 #define    start_cluster_cfd0_OFFSET          0
 #define    start_cluster_cfd0_NBBIT          16
 #define    start_cluster_cfd0_ALONE           1
 #define    start_cluster_cfd0_SIGNED          0
 /* end_cluster_cfd0               */
 #define    end_cluster_cfd0_ADDRESS         1878
 #define    end_cluster_cfd0_OFFSET            0
 #define    end_cluster_cfd0_NBBIT            16
 #define    end_cluster_cfd0_ALONE             1
 #define    end_cluster_cfd0_SIGNED            0
 /* confidence                     */
 #define    confidence_ADDRESS               1880
 #define    confidence_OFFSET                  0
 #define    confidence_NBBIT                   8
 #define    confidence_ALONE                   1
 #define    confidence_SIGNED                  0
 /* gain_cfd                       */
 #define    gain_cfd_ADDRESS                 1881
 #define    gain_cfd_OFFSET                    0
 #define    gain_cfd_NBBIT                     5
 #define    gain_cfd_ALONE                     1
 #define    gain_cfd_SIGNED                    0
 /* offset_cfd                     */
 #define    offset_cfd_ADDRESS               1882
 #define    offset_cfd_OFFSET                  0
 #define    offset_cfd_NBBIT                   3
 #define    offset_cfd_ALONE                   0
 #define    offset_cfd_SIGNED                  0
  #define           offset_cfd_m0_5                            0
  #define           offset_cfd_m0_25                           1
  #define           offset_cfd_0                               2
  #define           offset_cfd_p0_25                           3
  #define           offset_cfd_p0_5                            4
 /* init_noise                     */
 #define    init_noise_ADDRESS               1882
 #define    init_noise_OFFSET                  3
 #define    init_noise_NBBIT                   1
 #define    init_noise_ALONE                   0
 #define    init_noise_SIGNED                  0
  #define           init_noise_off                             0
  #define           init_noise_on                              1
 /* rst_cfd                        */
 #define    rst_cfd_ADDRESS                  1882
 #define    rst_cfd_OFFSET                     4
 #define    rst_cfd_NBBIT                      1
 #define    rst_cfd_ALONE                      0
 #define    rst_cfd_SIGNED                     0
  #define           rst_cfd_reset                              0
  #define           rst_cfd_run                                1
 /* sat_cfd                        */
 #define    sat_cfd_ADDRESS                  1883
 #define    sat_cfd_OFFSET                     0
 #define    sat_cfd_NBBIT                      3
 #define    sat_cfd_ALONE                      0
 #define    sat_cfd_SIGNED                     0
  #define           sat_cfd_0_75                               0
  #define           sat_cfd_1                                  1
  #define           sat_cfd_1_25                               2
  #define           sat_cfd_1_5                                3
  #define           sat_cfd_2                                  4
 /* deferred_noise                 */
 #define    deferred_noise_ADDRESS           1883
 #define    deferred_noise_OFFSET              3
 #define    deferred_noise_NBBIT               5
 #define    deferred_noise_ALONE               0
 #define    deferred_noise_SIGNED              0
 /* sigma2_reg                     */
 #define    sigma2_reg_ADDRESS               1884
 #define    sigma2_reg_OFFSET                  0
 #define    sigma2_reg_NBBIT                  24
 #define    sigma2_reg_ALONE                   1
 #define    sigma2_reg_SIGNED                  0
 /* start_cluster_cfd2             */
 #define    start_cluster_cfd2_ADDRESS       1888
 #define    start_cluster_cfd2_OFFSET          0
 #define    start_cluster_cfd2_NBBIT          16
 #define    start_cluster_cfd2_ALONE           1
 #define    start_cluster_cfd2_SIGNED          0
 /* end_cluster_cfd2               */
 #define    end_cluster_cfd2_ADDRESS         1890
 #define    end_cluster_cfd2_OFFSET            0
 #define    end_cluster_cfd2_NBBIT            16
 #define    end_cluster_cfd2_ALONE             1
 #define    end_cluster_cfd2_SIGNED            0
 /* sigma2_dsp                     */
 #define    sigma2_dsp_ADDRESS               1896
 #define    sigma2_dsp_OFFSET                  0
 #define    sigma2_dsp_NBBIT                  24
 #define    sigma2_dsp_ALONE                   1
 #define    sigma2_dsp_SIGNED                  0
 /* cpe                            */
 #define    cpe_ADDRESS                      1905
 #define    cpe_OFFSET                         0
 #define    cpe_NBBIT                          1
 #define    cpe_ALONE                          1
 #define    cpe_SIGNED                         0
  #define           cpe_off                                    0
  #define           cpe_on                                     1
 /* phi                            */
 #define    phi_ADDRESS                      1910
 #define    phi_OFFSET                         0
 #define    phi_NBBIT                         10
 #define    phi_ALONE                          1
 #define    phi_SIGNED                         0
 /* delta_phi                      */
 #define    delta_phi_ADDRESS                1916
 #define    delta_phi_OFFSET                   0
 #define    delta_phi_NBBIT                   10
 #define    delta_phi_ALONE                    1
 #define    delta_phi_SIGNED                   1
 /* hierarchy                      */
 #define    hierarchy_ADDRESS                1920
 #define    hierarchy_OFFSET                   0
 #define    hierarchy_NBBIT                    3
 #define    hierarchy_ALONE                    1
 #define    hierarchy_SIGNED                   0
  #define           hierarchy_none                             1
  #define           hierarchy_alfa1                            2
  #define           hierarchy_alfa2                            3
  #define           hierarchy_alfa4                            5
 /* ref_point_in                   */
 #define    ref_point_in_ADDRESS             1925
 #define    ref_point_in_OFFSET                0
 #define    ref_point_in_NBBIT                 7
 #define    ref_point_in_ALONE                 1
 #define    ref_point_in_SIGNED                0
 /* ref_point_out                  */
 #define    ref_point_out_ADDRESS            1926
 #define    ref_point_out_OFFSET               0
 #define    ref_point_out_NBBIT                7
 #define    ref_point_out_ALONE                1
 #define    ref_point_out_SIGNED               0
 /* crest_factor                   */
 #define    crest_factor_ADDRESS             1930
 #define    crest_factor_OFFSET                0
 #define    crest_factor_NBBIT                 2
 #define    crest_factor_ALONE                 1
 #define    crest_factor_SIGNED                0
  #define           crest_factor_5_db                          0
  #define           crest_factor_6_db                          1
  #define           crest_factor_7_db                          2
  #define           crest_factor_8_db                          3
 /* demap_scale                    */
 #define    demap_scale_ADDRESS              1931
 #define    demap_scale_OFFSET                 0
 #define    demap_scale_NBBIT                  8
 #define    demap_scale_ALONE                  1
 #define    demap_scale_SIGNED                 0
 /* quantize_mode                  */
 #define    quantize_mode_ADDRESS            1932
 #define    quantize_mode_OFFSET               0
 #define    quantize_mode_NBBIT                1
 #define    quantize_mode_ALONE                1
 #define    quantize_mode_SIGNED               0
  #define           quantize_mode_rounded                      0
  #define           quantize_mode_truncated                    1
 /* slope                          */
 #define    slope_ADDRESS                    1933
 #define    slope_OFFSET                       0
 #define    slope_NBBIT                        2
 #define    slope_ALONE                        1
 #define    slope_SIGNED                       0
  #define           slope_1_0                                  0
  #define           slope_2_0                                  1
  #define           slope_4_0                                  2
  #define           slope_8_0                                  3
 /* soft_bit_slope                 */
 #define    soft_bit_slope_ADDRESS           1936
 #define    soft_bit_slope_OFFSET              0
 #define    soft_bit_slope_NBBIT               9
 #define    soft_bit_slope_ALONE               1
 #define    soft_bit_slope_SIGNED              0
 /* forbid_softbit_eq0             */
 #define    forbid_softbit_eq0_ADDRESS       1938
 #define    forbid_softbit_eq0_OFFSET          0
 #define    forbid_softbit_eq0_NBBIT           1
 #define    forbid_softbit_eq0_ALONE           1
 #define    forbid_softbit_eq0_SIGNED          0
  #define           forbid_softbit_eq0_off                     0
  #define           forbid_softbit_eq0_on                      1
 /* gi_to_correl                   */
 #define    gi_to_correl_ADDRESS             1952
 #define    gi_to_correl_OFFSET                0
 #define    gi_to_correl_NBBIT                 3
 #define    gi_to_correl_ALONE                 1
 #define    gi_to_correl_SIGNED                0
  #define           gi_to_correl_1_32                          1
  #define           gi_to_correl_1_16                          2
  #define           gi_to_correl_1_8                           3
  #define           gi_to_correl_1_4                           4
 /* mode_to_correl                 */
 #define    mode_to_correl_ADDRESS           1956
 #define    mode_to_correl_OFFSET              0
 #define    mode_to_correl_NBBIT               4
 #define    mode_to_correl_ALONE               1
 #define    mode_to_correl_SIGNED              0
  #define           mode_to_correl_2k                         11
  #define           mode_to_correl_4k                         12
  #define           mode_to_correl_8k                         13
 /* rst_correl                     */
 #define    rst_correl_ADDRESS               1960
 #define    rst_correl_OFFSET                  0
 #define    rst_correl_NBBIT                   1
 #define    rst_correl_ALONE                   1
 #define    rst_correl_SIGNED                  0
  #define           rst_correl_reset                           1
  #define           rst_correl_run                             0
 /* start_search                   */
 #define    start_search_ADDRESS             1964
 #define    start_search_OFFSET                0
 #define    start_search_NBBIT                 1
 #define    start_search_ALONE                 1
 #define    start_search_SIGNED                0
  #define           start_search_start                         1
  #define           start_search_stop                          0
 /* force_cor                      */
 #define    force_cor_ADDRESS                1968
 #define    force_cor_OFFSET                   0
 #define    force_cor_NBBIT                    1
 #define    force_cor_ALONE                    1
 #define    force_cor_SIGNED                   0
  #define           force_cor_force                            1
  #define           force_cor_auto                             0
 /* fft_win_jitter                 */
 #define    fft_win_jitter_ADDRESS           1972
 #define    fft_win_jitter_OFFSET              0
 #define    fft_win_jitter_NBBIT               1
 #define    fft_win_jitter_ALONE               1
 #define    fft_win_jitter_SIGNED              0
  #define           fft_win_jitter_no_jitter                   1
  #define           fft_win_jitter_jitter                      0
 /* sel_index                      */
 #define    sel_index_ADDRESS                1976
 #define    sel_index_OFFSET                   0
 #define    sel_index_NBBIT                    1
 #define    sel_index_ALONE                    1
 #define    sel_index_SIGNED                   0
  #define           sel_index_rising                           0
  #define           sel_index_max                              1
 /* freq_shift_fir                 */
 #define    freq_shift_fir_ADDRESS           1980
 #define    freq_shift_fir_OFFSET              0
 #define    freq_shift_fir_NBBIT               2
 #define    freq_shift_fir_ALONE               1
 #define    freq_shift_fir_SIGNED              0
  #define           freq_shift_fir_no_shift                    0
  #define           freq_shift_fir_fs_on_4                     1
  #define           freq_shift_fir_fs_on_2                     2
  #define           freq_shift_fir_3fs_on_4                    3
 /* cor_threshold                  */
 #define    cor_threshold_ADDRESS            1984
 #define    cor_threshold_OFFSET               0
 #define    cor_threshold_NBBIT               10
 #define    cor_threshold_ALONE                1
 #define    cor_threshold_SIGNED               0
 /* rising_threshold               */
 #define    rising_threshold_ADDRESS         1988
 #define    rising_threshold_OFFSET            0
 #define    rising_threshold_NBBIT            10
 #define    rising_threshold_ALONE             1
 #define    rising_threshold_SIGNED            0
 /* falling_threshold              */
 #define    falling_threshold_ADDRESS        1992
 #define    falling_threshold_OFFSET           0
 #define    falling_threshold_NBBIT           10
 #define    falling_threshold_ALONE            1
 #define    falling_threshold_SIGNED           0
 /* gi_from_correl                 */
 #define    gi_from_correl_ADDRESS           1996
 #define    gi_from_correl_OFFSET              0
 #define    gi_from_correl_NBBIT               3
 #define    gi_from_correl_ALONE               1
 #define    gi_from_correl_SIGNED              0
  #define           gi_from_correl_1_32                        1
  #define           gi_from_correl_1_16                        2
  #define           gi_from_correl_1_8                         3
  #define           gi_from_correl_1_4                         4
 /* mode_from_correl               */
 #define    mode_from_correl_ADDRESS         2000
 #define    mode_from_correl_OFFSET            0
 #define    mode_from_correl_NBBIT             4
 #define    mode_from_correl_ALONE             1
 #define    mode_from_correl_SIGNED            0
  #define           mode_from_correl_2k                       11
  #define           mode_from_correl_4k                       12
  #define           mode_from_correl_8k                       13
 /* correl_agc_lock                */
 #define    correl_agc_lock_ADDRESS          2004
 #define    correl_agc_lock_OFFSET             0
 #define    correl_agc_lock_NBBIT              1
 #define    correl_agc_lock_ALONE              1
 #define    correl_agc_lock_SIGNED             0
  #define           correl_agc_lock_unlocked                   0
  #define           correl_agc_lock_locked                     1
 /* rising_index                   */
 #define    rising_index_ADDRESS             2008
 #define    rising_index_OFFSET                0
 #define    rising_index_NBBIT                14
 #define    rising_index_ALONE                 1
 #define    rising_index_SIGNED                0
 /* falling_index                  */
 #define    falling_index_ADDRESS            2012
 #define    falling_index_OFFSET               0
 #define    falling_index_NBBIT               14
 #define    falling_index_ALONE                1
 #define    falling_index_SIGNED               0
 /* max_peak                       */
 #define    max_peak_ADDRESS                 2016
 #define    max_peak_OFFSET                    0
 #define    max_peak_NBBIT                    10
 #define    max_peak_ALONE                     1
 #define    max_peak_SIGNED                    0
 /* en_top1                        */
 #define    en_top1_ADDRESS                  2032
 #define    en_top1_OFFSET                     0
 #define    en_top1_NBBIT                      1
 #define    en_top1_ALONE                      1
 #define    en_top1_SIGNED                     0
  #define           en_top1_disable                            0
  #define           en_top1_enable                             1
 /* en_top2                        */
 #define    en_top2_ADDRESS                  2036
 #define    en_top2_OFFSET                     0
 #define    en_top2_NBBIT                      1
 #define    en_top2_ALONE                      1
 #define    en_top2_SIGNED                     0
  #define           en_top2_disable                            0
  #define           en_top2_enable                             1
 /* en_top3                        */
 #define    en_top3_ADDRESS                  2040
 #define    en_top3_OFFSET                     0
 #define    en_top3_NBBIT                      1
 #define    en_top3_ALONE                      1
 #define    en_top3_SIGNED                     0
  #define           en_top3_disable                            0
  #define           en_top3_enable                             1
 /* en_top4                        */
 #define    en_top4_ADDRESS                  2048
 #define    en_top4_OFFSET                     0
 #define    en_top4_NBBIT                      1
 #define    en_top4_ALONE                      1
 #define    en_top4_SIGNED                     0
  #define           en_top4_disable                            0
  #define           en_top4_enable                             1
 /* use_ext_top                    */
 #define    use_ext_top_ADDRESS              2052
 #define    use_ext_top_OFFSET                 0
 #define    use_ext_top_NBBIT                  1
 #define    use_ext_top_ALONE                  1
 #define    use_ext_top_SIGNED                 0
  #define           use_ext_top_internal                       0
  #define           use_ext_top_external                       1
 /* rst_cnt_top                    */
 #define    rst_cnt_top_ADDRESS              2056
 #define    rst_cnt_top_OFFSET                 0
 #define    rst_cnt_top_NBBIT                  1
 #define    rst_cnt_top_ALONE                  1
 #define    rst_cnt_top_SIGNED                 0
  #define           rst_cnt_top_run                            0
  #define           rst_cnt_top_reset                          1
 /* rst_cnt_symb                   */
 #define    rst_cnt_symb_ADDRESS             2060
 #define    rst_cnt_symb_OFFSET                0
 #define    rst_cnt_symb_NBBIT                 1
 #define    rst_cnt_symb_ALONE                 1
 #define    rst_cnt_symb_SIGNED                0
  #define           rst_cnt_symb_run                           0
  #define           rst_cnt_symb_reset                         1
 /* cnt_symb                       */
 #define    cnt_symb_ADDRESS                 2064
 #define    cnt_symb_OFFSET                    0
 #define    cnt_symb_NBBIT                     9
 #define    cnt_symb_ALONE                     1
 #define    cnt_symb_SIGNED                    0
 /* top_shift                      */
 #define    top_shift_ADDRESS                2068
 #define    top_shift_OFFSET                   0
 #define    top_shift_NBBIT                   15
 #define    top_shift_ALONE                    1
 #define    top_shift_SIGNED                   1
 /* symb_length                    */
 #define    symb_length_ADDRESS              2072
 #define    symb_length_OFFSET                 0
 #define    symb_length_NBBIT                 14
 #define    symb_length_ALONE                  1
 #define    symb_length_SIGNED                 0
 /* latency1                       */
 #define    latency1_ADDRESS                 2076
 #define    latency1_OFFSET                    0
 #define    latency1_NBBIT                    14
 #define    latency1_ALONE                     1
 #define    latency1_SIGNED                    0
 /* latency2                       */
 #define    latency2_ADDRESS                 2080
 #define    latency2_OFFSET                    0
 #define    latency2_NBBIT                    14
 #define    latency2_ALONE                     1
 #define    latency2_SIGNED                    0
 /* latency3                       */
 #define    latency3_ADDRESS                 2084
 #define    latency3_OFFSET                    0
 #define    latency3_NBBIT                    14
 #define    latency3_ALONE                     1
 #define    latency3_SIGNED                    0
 /* latency4                       */
 #define    latency4_ADDRESS                 2088
 #define    latency4_OFFSET                    0
 #define    latency4_NBBIT                    14
 #define    latency4_ALONE                     1
 #define    latency4_SIGNED                    0
 /* start_dma                      */
 #define    start_dma_ADDRESS                2096
 #define    start_dma_OFFSET                   0
 #define    start_dma_NBBIT                    4
 #define    start_dma_ALONE                    1
 #define    start_dma_SIGNED                   0
 /* rst_dma1                       */
 #define    rst_dma1_ADDRESS                 2100
 #define    rst_dma1_OFFSET                    0
 #define    rst_dma1_NBBIT                     1
 #define    rst_dma1_ALONE                     1
 #define    rst_dma1_SIGNED                    0
  #define           rst_dma1_reset                             1
  #define           rst_dma1_run                               0
 /* wren_dma1                      */
 #define    wren_dma1_ADDRESS                2104
 #define    wren_dma1_OFFSET                   0
 #define    wren_dma1_NBBIT                    1
 #define    wren_dma1_ALONE                    1
 #define    wren_dma1_SIGNED                   0
  #define           wren_dma1_read                             0
  #define           wren_dma1_write                            1
 /* dma_mode1                      */
 #define    dma_mode1_ADDRESS                2108
 #define    dma_mode1_OFFSET                   0
 #define    dma_mode1_NBBIT                    2
 #define    dma_mode1_ALONE                    1
 #define    dma_mode1_SIGNED                   0
  #define           dma_mode1_one_burst                        0
  #define           dma_mode1_circular                         1
  #define           dma_mode1_finish_circular                  2
 /* decim1                         */
 #define    decim1_ADDRESS                   2112
 #define    decim1_OFFSET                      0
 #define    decim1_NBBIT                       3
 #define    decim1_ALONE                       1
 #define    decim1_SIGNED                      0
  #define           decim1_decim_by_2                          1
  #define           decim1_decim_by_4                          2
  #define           decim1_decim_by_8                          3
  #define           decim1_decim_by_16                         4
  #define           decim1_decim_by_32                         5
  #define           decim1_decim_by_64                         6
  #define           decim1_decim_by_128                        7
  #define           decim1_no_decimation                       0
 /* start_dma1                     */
 #define    start_dma1_ADDRESS               2116
 #define    start_dma1_OFFSET                  0
 #define    start_dma1_NBBIT                   1
 #define    start_dma1_ALONE                   1
 #define    start_dma1_SIGNED                  0
  #define           start_dma1_start                           1
  #define           start_dma1_stop                            0
 /* rst_dma2                       */
 #define    rst_dma2_ADDRESS                 2120
 #define    rst_dma2_OFFSET                    0
 #define    rst_dma2_NBBIT                     1
 #define    rst_dma2_ALONE                     1
 #define    rst_dma2_SIGNED                    0
  #define           rst_dma2_reset                             1
  #define           rst_dma2_run                               0
 /* wren_dma2                      */
 #define    wren_dma2_ADDRESS                2124
 #define    wren_dma2_OFFSET                   0
 #define    wren_dma2_NBBIT                    1
 #define    wren_dma2_ALONE                    1
 #define    wren_dma2_SIGNED                   0
  #define           wren_dma2_read                             0
  #define           wren_dma2_write                            1
 /* dma_mode2                      */
 #define    dma_mode2_ADDRESS                2128
 #define    dma_mode2_OFFSET                   0
 #define    dma_mode2_NBBIT                    2
 #define    dma_mode2_ALONE                    1
 #define    dma_mode2_SIGNED                   0
  #define           dma_mode2_one_burst                        0
  #define           dma_mode2_circular                         1
  #define           dma_mode2_finish_circular                  2
 /* decim2                         */
 #define    decim2_ADDRESS                   2132
 #define    decim2_OFFSET                      0
 #define    decim2_NBBIT                       3
 #define    decim2_ALONE                       1
 #define    decim2_SIGNED                      0
  #define           decim2_decim_by_2                          1
  #define           decim2_decim_by_4                          2
  #define           decim2_decim_by_8                          3
  #define           decim2_decim_by_16                         4
  #define           decim2_decim_by_32                         5
  #define           decim2_decim_by_64                         6
  #define           decim2_decim_by_128                        7
  #define           decim2_no_decimation                       0
 /* start_dma2                     */
 #define    start_dma2_ADDRESS               2136
 #define    start_dma2_OFFSET                  0
 #define    start_dma2_NBBIT                   1
 #define    start_dma2_ALONE                   1
 #define    start_dma2_SIGNED                  0
  #define           start_dma2_start                           1
  #define           start_dma2_stop                            0
 /* rst_dma3                       */
 #define    rst_dma3_ADDRESS                 2140
 #define    rst_dma3_OFFSET                    0
 #define    rst_dma3_NBBIT                     1
 #define    rst_dma3_ALONE                     1
 #define    rst_dma3_SIGNED                    0
  #define           rst_dma3_reset                             1
  #define           rst_dma3_run                               0
 /* wren_dma3                      */
 #define    wren_dma3_ADDRESS                2144
 #define    wren_dma3_OFFSET                   0
 #define    wren_dma3_NBBIT                    1
 #define    wren_dma3_ALONE                    1
 #define    wren_dma3_SIGNED                   0
  #define           wren_dma3_read                             0
  #define           wren_dma3_write                            1
 /* dma_mode3                      */
 #define    dma_mode3_ADDRESS                2148
 #define    dma_mode3_OFFSET                   0
 #define    dma_mode3_NBBIT                    2
 #define    dma_mode3_ALONE                    1
 #define    dma_mode3_SIGNED                   0
  #define           dma_mode3_one_burst                        0
  #define           dma_mode3_circular                         1
  #define           dma_mode3_finish_circular                  2
 /* decim3                         */
 #define    decim3_ADDRESS                   2152
 #define    decim3_OFFSET                      0
 #define    decim3_NBBIT                       3
 #define    decim3_ALONE                       1
 #define    decim3_SIGNED                      0
  #define           decim3_decim_by_2                          1
  #define           decim3_decim_by_4                          2
  #define           decim3_decim_by_8                          3
  #define           decim3_decim_by_16                         4
  #define           decim3_decim_by_32                         5
  #define           decim3_decim_by_64                         6
  #define           decim3_decim_by_128                        7
  #define           decim3_no_decimation                       0
 /* start_dma3                     */
 #define    start_dma3_ADDRESS               2156
 #define    start_dma3_OFFSET                  0
 #define    start_dma3_NBBIT                   1
 #define    start_dma3_ALONE                   1
 #define    start_dma3_SIGNED                  0
  #define           start_dma3_start                           1
  #define           start_dma3_stop                            0
 /* rst_dma4                       */
 #define    rst_dma4_ADDRESS                 2160
 #define    rst_dma4_OFFSET                    0
 #define    rst_dma4_NBBIT                     1
 #define    rst_dma4_ALONE                     1
 #define    rst_dma4_SIGNED                    0
  #define           rst_dma4_reset                             1
  #define           rst_dma4_run                               0
 /* wren_dma4                      */
 #define    wren_dma4_ADDRESS                2164
 #define    wren_dma4_OFFSET                   0
 #define    wren_dma4_NBBIT                    1
 #define    wren_dma4_ALONE                    1
 #define    wren_dma4_SIGNED                   0
  #define           wren_dma4_read                             0
  #define           wren_dma4_write                            1
 /* dma_mode4                      */
 #define    dma_mode4_ADDRESS                2168
 #define    dma_mode4_OFFSET                   0
 #define    dma_mode4_NBBIT                    2
 #define    dma_mode4_ALONE                    1
 #define    dma_mode4_SIGNED                   0
  #define           dma_mode4_one_burst                        0
  #define           dma_mode4_circular                         1
  #define           dma_mode4_finish_circular                  2
 /* decim4                         */
 #define    decim4_ADDRESS                   2172
 #define    decim4_OFFSET                      0
 #define    decim4_NBBIT                       3
 #define    decim4_ALONE                       1
 #define    decim4_SIGNED                      0
  #define           decim4_decim_by_2                          1
  #define           decim4_decim_by_4                          2
  #define           decim4_decim_by_8                          3
  #define           decim4_decim_by_16                         4
  #define           decim4_decim_by_32                         5
  #define           decim4_decim_by_64                         6
  #define           decim4_decim_by_128                        7
  #define           decim4_no_decimation                       0
 /* start_dma4                     */
 #define    start_dma4_ADDRESS               2176
 #define    start_dma4_OFFSET                  0
 #define    start_dma4_NBBIT                   1
 #define    start_dma4_ALONE                   1
 #define    start_dma4_SIGNED                  0
  #define           start_dma4_start                           1
  #define           start_dma4_stop                            0
 /* start_addr1                    */
 #define    start_addr1_ADDRESS              2180
 #define    start_addr1_OFFSET                 0
 #define    start_addr1_NBBIT                 16
 #define    start_addr1_ALONE                  1
 #define    start_addr1_SIGNED                 0
 /* bank_length1                   */
 #define    bank_length1_ADDRESS             2184
 #define    bank_length1_OFFSET                0
 #define    bank_length1_NBBIT                17
 #define    bank_length1_ALONE                 1
 #define    bank_length1_SIGNED                0
 /* start_addr2                    */
 #define    start_addr2_ADDRESS              2188
 #define    start_addr2_OFFSET                 0
 #define    start_addr2_NBBIT                 16
 #define    start_addr2_ALONE                  1
 #define    start_addr2_SIGNED                 0
 /* bank_length2                   */
 #define    bank_length2_ADDRESS             2192
 #define    bank_length2_OFFSET                0
 #define    bank_length2_NBBIT                17
 #define    bank_length2_ALONE                 1
 #define    bank_length2_SIGNED                0
 /* start_addr3                    */
 #define    start_addr3_ADDRESS              2196
 #define    start_addr3_OFFSET                 0
 #define    start_addr3_NBBIT                 16
 #define    start_addr3_ALONE                  1
 #define    start_addr3_SIGNED                 0
 /* bank_length3                   */
 #define    bank_length3_ADDRESS             2200
 #define    bank_length3_OFFSET                0
 #define    bank_length3_NBBIT                17
 #define    bank_length3_ALONE                 1
 #define    bank_length3_SIGNED                0
 /* start_addr4                    */
 #define    start_addr4_ADDRESS              2204
 #define    start_addr4_OFFSET                 0
 #define    start_addr4_NBBIT                 16
 #define    start_addr4_ALONE                  1
 #define    start_addr4_SIGNED                 0
 /* bank_length4                   */
 #define    bank_length4_ADDRESS             2208
 #define    bank_length4_OFFSET                0
 #define    bank_length4_NBBIT                17
 #define    bank_length4_ALONE                 1
 #define    bank_length4_SIGNED                0
 /* bank_number1                   */
 #define    bank_number1_ADDRESS             2212
 #define    bank_number1_OFFSET                0
 #define    bank_number1_NBBIT                 1
 #define    bank_number1_ALONE                 1
 #define    bank_number1_SIGNED                0
  #define           bank_number1_first                         0
  #define           bank_number1_second                        1
 /* status_dma1                    */
 #define    status_dma1_ADDRESS              2216
 #define    status_dma1_OFFSET                 0
 #define    status_dma1_NBBIT                  2
 #define    status_dma1_ALONE                  1
 #define    status_dma1_SIGNED                 0
  #define           status_dma1_wait_start                     1
  #define           status_dma1_processing                     2
  #define           status_dma1_finished                       3
  #define           status_dma1_waiting                        0
 /* bank_number2                   */
 #define    bank_number2_ADDRESS             2220
 #define    bank_number2_OFFSET                0
 #define    bank_number2_NBBIT                 1
 #define    bank_number2_ALONE                 1
 #define    bank_number2_SIGNED                0
  #define           bank_number2_first                         0
  #define           bank_number2_second                        1
 /* status_dma2                    */
 #define    status_dma2_ADDRESS              2224
 #define    status_dma2_OFFSET                 0
 #define    status_dma2_NBBIT                  2
 #define    status_dma2_ALONE                  1
 #define    status_dma2_SIGNED                 0
  #define           status_dma2_wait_start                     1
  #define           status_dma2_processing                     2
  #define           status_dma2_finished                       3
  #define           status_dma2_waiting                        0
 /* bank_number3                   */
 #define    bank_number3_ADDRESS             2228
 #define    bank_number3_OFFSET                0
 #define    bank_number3_NBBIT                 1
 #define    bank_number3_ALONE                 1
 #define    bank_number3_SIGNED                0
  #define           bank_number3_first                         0
  #define           bank_number3_second                        1
 /* status_dma3                    */
 #define    status_dma3_ADDRESS              2232
 #define    status_dma3_OFFSET                 0
 #define    status_dma3_NBBIT                  2
 #define    status_dma3_ALONE                  1
 #define    status_dma3_SIGNED                 0
  #define           status_dma3_wait_start                     1
  #define           status_dma3_processing                     2
  #define           status_dma3_finished                       3
  #define           status_dma3_waiting                        0
 /* bank_number4                   */
 #define    bank_number4_ADDRESS             2236
 #define    bank_number4_OFFSET                0
 #define    bank_number4_NBBIT                 1
 #define    bank_number4_ALONE                 1
 #define    bank_number4_SIGNED                0
  #define           bank_number4_first                         0
  #define           bank_number4_second                        1
 /* status_dma4                    */
 #define    status_dma4_ADDRESS              2240
 #define    status_dma4_OFFSET                 0
 #define    status_dma4_NBBIT                  2
 #define    status_dma4_ALONE                  1
 #define    status_dma4_SIGNED                 0
  #define           status_dma4_wait_start                     1
  #define           status_dma4_processing                     2
  #define           status_dma4_finished                       3
  #define           status_dma4_waiting                        0
 /* incr_addr1_uns                 */
 #define    incr_addr1_uns_ADDRESS           2244
 #define    incr_addr1_uns_OFFSET              0
 #define    incr_addr1_uns_NBBIT               2
 #define    incr_addr1_uns_ALONE               1
 #define    incr_addr1_uns_SIGNED              0
  #define           incr_addr1_uns_increments_by_1             0
  #define           incr_addr1_uns_increments_by_2             1
  #define           incr_addr1_uns_increments_by_4             2
  #define           incr_addr1_uns_increments_by_8             3
 /* incr_addr2_uns                 */
 #define    incr_addr2_uns_ADDRESS           2248
 #define    incr_addr2_uns_OFFSET              0
 #define    incr_addr2_uns_NBBIT               2
 #define    incr_addr2_uns_ALONE               1
 #define    incr_addr2_uns_SIGNED              0
  #define           incr_addr2_uns_increments_by_1             0
  #define           incr_addr2_uns_increments_by_2             1
  #define           incr_addr2_uns_increments_by_4             2
  #define           incr_addr2_uns_increments_by_8             3
 /* incr_addr3_uns                 */
 #define    incr_addr3_uns_ADDRESS           2252
 #define    incr_addr3_uns_OFFSET              0
 #define    incr_addr3_uns_NBBIT               2
 #define    incr_addr3_uns_ALONE               1
 #define    incr_addr3_uns_SIGNED              0
  #define           incr_addr3_uns_increments_by_1             0
  #define           incr_addr3_uns_increments_by_2             1
  #define           incr_addr3_uns_increments_by_4             2
  #define           incr_addr3_uns_increments_by_8             3
 /* incr_addr4_uns                 */
 #define    incr_addr4_uns_ADDRESS           2256
 #define    incr_addr4_uns_OFFSET              0
 #define    incr_addr4_uns_NBBIT               2
 #define    incr_addr4_uns_ALONE               1
 #define    incr_addr4_uns_SIGNED              0
  #define           incr_addr4_uns_increments_by_1             0
  #define           incr_addr4_uns_increments_by_2             1
  #define           incr_addr4_uns_increments_by_4             2
  #define           incr_addr4_uns_increments_by_8             3
 /* sel_tst_frontend               */
 #define    sel_tst_frontend_ADDRESS         2272
 #define    sel_tst_frontend_OFFSET            0
 #define    sel_tst_frontend_NBBIT             4
 #define    sel_tst_frontend_ALONE             1
 #define    sel_tst_frontend_SIGNED            0
  #define           sel_tst_frontend_tst_in                    0
  #define           sel_tst_frontend_status                    1
  #define           sel_tst_frontend_agc_pow_max               2
  #define           sel_tst_frontend_agc_er_fil                3
  #define           sel_tst_frontend_aaf_agc_cmd               4
  #define           sel_tst_frontend_aaf_pow_max               5
  #define           sel_tst_frontend_aaf_er_fil                6
  #define           sel_tst_frontend_i_adc_sgn                 7
  #define           sel_tst_frontend_q_adc_sgn                 8
  #define           sel_tst_frontend_inf_out                   9
  #define           sel_tst_frontend_phi_cor                  10
 /* sel_tst_demod                  */
 #define    sel_tst_demod_ADDRESS            2276
 #define    sel_tst_demod_OFFSET               0
 #define    sel_tst_demod_NBBIT                4
 #define    sel_tst_demod_ALONE                1
 #define    sel_tst_demod_SIGNED               0
  #define           sel_tst_demod_tst_in                       0
  #define           sel_tst_demod_i_fir1                       1
  #define           sel_tst_demod_ifir2                        2
  #define           sel_tst_demod_ibit_rev                     3
  #define           sel_tst_demod_aci_er_fil                   4
  #define           sel_tst_demod_aci_agc_cmd                  5
  #define           sel_tst_demod_i_fft_out                    6
  #define           sel_tst_demod_imp_noise                    7
  #define           sel_tst_demod_qam_tim_corr                 8
  #define           sel_tst_demod_qam_freq_cor                 9
  #define           sel_tst_demod_qam_status                  10
 /* sel_tst_eq                     */
 #define    sel_tst_eq_ADDRESS               2280
 #define    sel_tst_eq_OFFSET                  0
 #define    sel_tst_eq_NBBIT                   5
 #define    sel_tst_eq_ALONE                   1
 #define    sel_tst_eq_SIGNED                  0
  #define           sel_tst_eq_tst_in                          0
  #define           sel_tst_eq_intf_i                          1
  #define           sel_tst_eq_intf_q                          2
  #define           sel_tst_eq_scatt_i                         3
  #define           sel_tst_eq_scatt_q                         4
  #define           sel_tst_eq_time_i                          5
  #define           sel_tst_eq_time_q                          6
  #define           sel_tst_eq_freq_i                          7
  #define           sel_tst_eq_freq_q                          8
  #define           sel_tst_eq_cor_i                           9
  #define           sel_tst_eq_cor_q                          10
  #define           sel_tst_eq_conf                           11
  #define           sel_tst_eq_sigma2                         12
  #define           sel_tst_eq_mean_power                     13
 /* sel_tst_equal                  */
 #define    sel_tst_equal_ADDRESS            2284
 #define    sel_tst_equal_OFFSET               0
 #define    sel_tst_equal_NBBIT                3
 #define    sel_tst_equal_ALONE                1
 #define    sel_tst_equal_SIGNED               0
  #define           sel_tst_equal_tst_in                       0
  #define           sel_tst_equal_status                       1
  #define           sel_tst_equal_c_n                          2
  #define           sel_tst_equal_freq                         3
  #define           sel_tst_equal_coef_i                       4
  #define           sel_tst_equal_symb_i                       5
  #define           sel_tst_equal_hard_bits                    6
 /* sel_tst_synchro                */
 #define    sel_tst_synchro_ADDRESS          2288
 #define    sel_tst_synchro_OFFSET             0
 #define    sel_tst_synchro_NBBIT              5
 #define    sel_tst_synchro_ALONE              1
 #define    sel_tst_synchro_SIGNED             0
  #define           sel_tst_synchro_tst_in                     0
  #define           sel_tst_synchro_input_data                 1
  #define           sel_tst_synchro_cor                        2
  #define           sel_tst_synchro_corfilt                    3
  #define           sel_tst_synchro_corf                       4
  #define           sel_tst_synchro_agc_lock                   5
  #define           sel_tst_synchro_top_in                     6
  #define           sel_tst_synchro_timer_lock_top             7
  #define           sel_tst_synchro_symb_top2                  8
  #define           sel_tst_synchro_symb_top3                  9
  #define           sel_tst_synchro_symb_top4                 10
  #define           sel_tst_synchro_dma1                      11
  #define           sel_tst_synchro_dma2                      12
  #define           sel_tst_synchro_dma3                      13
  #define           sel_tst_synchro_data3_from_dma            14
  #define           sel_tst_synchro_data4_from_dma            15
  #define           sel_tst_synchro_ahb_gpio1                 16
  #define           sel_tst_synchro_ahb_gpio2                 17
  #define           sel_tst_synchro_ahb_gpio3                 18
 /* sel_tst_leon                   */
 #define    sel_tst_leon_ADDRESS             2292
 #define    sel_tst_leon_OFFSET                0
 #define    sel_tst_leon_NBBIT                 4
 #define    sel_tst_leon_ALONE                 1
 #define    sel_tst_leon_SIGNED                0
  #define           sel_tst_leon_tst_in                        0
  #define           sel_tst_leon_program_counter_clk           1
  #define           sel_tst_leon_program_counter               2
 /* sel_tst_fec                    */
 #define    sel_tst_fec_ADDRESS              2296
 #define    sel_tst_fec_OFFSET                 0
 #define    sel_tst_fec_NBBIT                  3
 #define    sel_tst_fec_ALONE                  1
 #define    sel_tst_fec_SIGNED                 0
  #define           sel_tst_fec_tst_in                         0
  #define           sel_tst_fec_symbol_deint                   1
  #define           sel_tst_fec_demapper                       2
  #define           sel_tst_fec_bit_deint                      3
  #define           sel_tst_fec_viterbi_psync                  4
  #define           sel_tst_fec_reed_solomon                   5
  #define           sel_tst_fec_desc_fec_status                6
  #define           sel_tst_fec_mpeg_ts                        7
 /* sel_clk_tst                    */
 #define    sel_clk_tst_ADDRESS              2306
 #define    sel_clk_tst_OFFSET                 0
 #define    sel_clk_tst_NBBIT                  2
 #define    sel_clk_tst_ALONE                  0
 #define    sel_clk_tst_SIGNED                 0
  #define           sel_clk_tst_clk_epb                        0
  #define           sel_clk_tst_clk_samp                       1
  #define           sel_clk_tst_clk_fsx4                       2
  #define           sel_clk_tst_clk_dsp                        3
 /* inv_clk_tst                    */
 #define    inv_clk_tst_ADDRESS              2306
 #define    inv_clk_tst_OFFSET                 2
 #define    inv_clk_tst_NBBIT                  1
 #define    inv_clk_tst_ALONE                  0
 #define    inv_clk_tst_SIGNED                 0
  #define           inv_clk_tst_n                              0
  #define           inv_clk_tst_y                              1
 /* enable                         */
 #define    enable_ADDRESS                   2320
 #define    enable_OFFSET                      0
 #define    enable_NBBIT                       1
 #define    enable_ALONE                       1
 #define    enable_SIGNED                      0
  #define           enable_disable                             0
  #define           enable_enable                              1
 /* word_size                      */
 #define    word_size_ADDRESS                2324
 #define    word_size_OFFSET                   0
 #define    word_size_NBBIT                    2
 #define    word_size_ALONE                    0
 #define    word_size_SIGNED                   0
  #define           word_size_6bit                             0
  #define           word_size_8bit                             1
  #define           word_size_10bit                            2
  #define           word_size_12bit                            3
 /* scram_enable                   */
 #define    scram_enable_ADDRESS             2324
 #define    scram_enable_OFFSET                2
 #define    scram_enable_NBBIT                 1
 #define    scram_enable_ALONE                 0
 #define    scram_enable_SIGNED                0
  #define           scram_enable_disable                       0
  #define           scram_enable_enable                        1
 /* error_detect_enable            */
 #define    error_detect_enable_ADDRESS      2324
 #define    error_detect_enable_OFFSET         3
 #define    error_detect_enable_NBBIT          1
 #define    error_detect_enable_ALONE          0
 #define    error_detect_enable_SIGNED         0
  #define           error_detect_enable_disable                0
  #define           error_detect_enable_enable                 1
 /* e2e_test_enable                */
 #define    e2e_test_enable_ADDRESS          2324
 #define    e2e_test_enable_OFFSET             4
 #define    e2e_test_enable_NBBIT              1
 #define    e2e_test_enable_ALONE              0
 #define    e2e_test_enable_SIGNED             0
  #define           e2e_test_enable_disable                    0
  #define           e2e_test_enable_enable                     1
 /* frame_sync_detect              */
 #define    frame_sync_detect_ADDRESS        2328
 #define    frame_sync_detect_OFFSET           0
 #define    frame_sync_detect_NBBIT            1
 #define    frame_sync_detect_ALONE            0
 #define    frame_sync_detect_SIGNED           0
  #define           frame_sync_detect_not_detected             0
  #define           frame_sync_detect_detected                 1
 /* scram_sync_detect              */
 #define    scram_sync_detect_ADDRESS        2328
 #define    scram_sync_detect_OFFSET           1
 #define    scram_sync_detect_NBBIT            1
 #define    scram_sync_detect_ALONE            0
 #define    scram_sync_detect_SIGNED           0
  #define           scram_sync_detect_not_detected             0
  #define           scram_sync_detect_detected                 1
 /* code_error_count               */
 #define    code_error_count_ADDRESS         2332
 #define    code_error_count_OFFSET            0
 #define    code_error_count_NBBIT            16
 #define    code_error_count_ALONE             1
 #define    code_error_count_SIGNED            0
 /* e2e_error_count                */
 #define    e2e_error_count_ADDRESS          2336
 #define    e2e_error_count_OFFSET             0
 #define    e2e_error_count_NBBIT             16
 #define    e2e_error_count_ALONE              1
 #define    e2e_error_count_SIGNED             0
 /* chip_mode                      */
 #define    chip_mode_ADDRESS                  0
 #define    chip_mode_OFFSET                   0
 #define    chip_mode_NBBIT                    7
 #define    chip_mode_ALONE                    1
 #define    chip_mode_SIGNED                   0
  #define           chip_mode_off                              0
  #define           chip_mode_pll_ext                         32
  #define           chip_mode_pll_xtal                        33
  #define           chip_mode_pll_rssi                        34
  #define           chip_mode_sdi_ext                         44
  #define           chip_mode_sdi_rssi                        46
  #define           chip_mode_gpio_ext                        48
  #define           chip_mode_gpio_xtal                       49
  #define           chip_mode_gpio_rssi1                      50
  #define           chip_mode_gpio_rssi2                      51

 /* special definitions used for firmware control */
 /* dsp_mode                     */
 #define    dsp_mode_ADDRESS                   gp_reg0_ADDRESS
 #define    dsp_mode_OFFSET                    28
 #define    dsp_mode_NBBIT                      4
 #define    dsp_mode_ALONE                      0
 #define    dsp_mode_SIGNED                     0
  #define           dsp_mode_dvb_t                         0
  #define           dsp_mode_tune                          4
  #define           dsp_mode_scan                          1
 /* dvb_c_modulation                     */
 #define    dvb_c_modulation_ADDRESS            gp_reg0_ADDRESS
 #define    dvb_c_modulation_OFFSET            12
 #define    dvb_c_modulation_NBBIT              4
 #define    dvb_c_modulation_ALONE              0
 #define    dvb_c_modulation_SIGNED             0
 /* pause_scan                     */
 #define    pause_scan_ADDRESS                   gp_reg0_ADDRESS
 #define    pause_scan_OFFSET                   13
 #define    pause_scan_NBBIT                     1
 #define    pause_scan_ALONE                     0
 #define    pause_scan_SIGNED                    0
 /* analog_bw                     */
 #define    analog_bw_ADDRESS                    gp_reg0_ADDRESS
 #define    analog_bw_OFFSET                    14
 #define    analog_bw_NBBIT                      1
 #define    analog_bw_ALONE                      0
 #define    analog_bw_SIGNED                     0
  #define           analog_bw_6mhz                         0
  #define           analog_bw_7mhz                         1
  #define           analog_bw_8mhz                         1
 /* output_analog                     */
 #define    output_analog_ADDRESS               gp_reg0_ADDRESS
 #define    output_analog_OFFSET                12
 #define    output_analog_NBBIT                  1
 #define    output_analog_ALONE                  0
 #define    output_analog_SIGNED                 0
 /* scan_ack                     */
 #define    scan_ack_ADDRESS                    gp_reg0_ADDRESS
 #define    scan_ack_OFFSET                      0
 #define    scan_ack_NBBIT                       1
 #define    scan_ack_ALONE                       0
 #define    scan_ack_SIGNED                      0
 /* scan_step                    */
 #define    scan_step_ADDRESS                   bandwidth_ADDRESS
 #define    scan_step_OFFSET                     bandwidth_OFFSET
 #define    scan_step_NBBIT                      bandwidth_NBBIT
 #define    scan_step_ALONE                      bandwidth_ALONE
 #define    scan_step_SIGNED                     bandwidth_SIGNED
 /* min_symbols                     */
 #define    min_symbols_ADDRESS                 gp_reg0_ADDRESS
 #define    min_symbols_OFFSET                   0
 #define    min_symbols_NBBIT                    8
 #define    min_symbols_ALONE                    0
 #define    min_symbols_SIGNED                   0
 /* valid_freq                     */
 #define    valid_freq_ADDRESS                   gp_reg0_ADDRESS
 #define    valid_freq_OFFSET                   31
 #define    valid_freq_NBBIT                     1
 #define    valid_freq_ALONE                     0
 #define    valid_freq_SIGNED                    0
 /* ber_threshold_power                    */
 #define    ber_threshold_power_ADDRESS         gp_reg1_ADDRESS
 #define    ber_threshold_power_OFFSET           8
 #define    ber_threshold_power_NBBIT            4
 #define    ber_threshold_power_ALONE            0
 #define    ber_threshold_power_SIGNED           0
 /* first_rf                    */
 #define    first_rf_ADDRESS                    gp_reg1_ADDRESS
 #define    first_rf_OFFSET                      gp_reg1_OFFSET
 #define    first_rf_NBBIT                       gp_reg1_NBBIT
 #define    first_rf_ALONE                       gp_reg1_ALONE
 #define    first_rf_SIGNED                      gp_reg1_SIGNED
 /* last_rf                    */
 #define    last_rf_ADDRESS                    gp_reg2_ADDRESS
 #define    last_rf_OFFSET                      gp_reg2_OFFSET
 #define    last_rf_NBBIT                       gp_reg2_NBBIT
 #define    last_rf_ALONE                       gp_reg2_ALONE
 #define    last_rf_SIGNED                      gp_reg2_SIGNED
 /* demod_ref_freq_khz                     */
 #define    demod_ref_freq_khz_ADDRESS          timing_corr_t_ADDRESS
 #define    demod_ref_freq_khz_OFFSET            0
 #define    demod_ref_freq_khz_NBBIT            32
 #define    demod_ref_freq_khz_ALONE             0
 #define    demod_ref_freq_khz_SIGNED            0
 /* scan_finished                     */
 #define    scan_finished_ADDRESS                gp_reg0_ADDRESS
 #define    scan_finished_OFFSET                30
 #define    scan_finished_NBBIT                  1
 #define    scan_finished_ALONE                  0
 #define    scan_finished_SIGNED                 0
 /* tuner_ref_freq_hz                     */
 #define    tuner_ref_freq_hz_ADDRESS            freq_corr_t_ADDRESS
 #define    tuner_ref_freq_hz_OFFSET             0
 #define    tuner_ref_freq_hz_NBBIT             32
 #define    tuner_ref_freq_hz_ALONE              0
 #define    tuner_ref_freq_hz_SIGNED             0
 /* rst_demod                      */
 #define    rst_demod_ADDRESS                205
 #define    rst_demod_OFFSET                   1
 #define    rst_demod_NBBIT                    1
 #define    rst_demod_ALONE                    0
 #define    rst_demod_SIGNED                   0
  #define           rst_demod_reset                            0
  #define           rst_demod_run                              1
 /* rst_equal                      */
 #define    rst_equal_ADDRESS                205
 #define    rst_equal_OFFSET                   2
 #define    rst_equal_NBBIT                    1
 #define    rst_equal_ALONE                    0
 #define    rst_equal_SIGNED                   0
  #define           rst_equal_reset                            0
  #define           rst_equal_run                              1
 /* rst_fec                        */
 #define    rst_fec_ADDRESS                  205
 #define    rst_fec_OFFSET                     3
 #define    rst_fec_NBBIT                      1
 #define    rst_fec_ALONE                      0
 #define    rst_fec_SIGNED                     0
  #define           rst_fec_reset                              0
  #define           rst_fec_run                                1

#endif /* end of _L1_S1216x_Defines_H_ */



